diff mbox series

[v3,2/2] hw/char: sifive_uart

Message ID 20210613141222.548357-3-lukas.juenger@greensocs.com (mailing list archive)
State New, archived
Headers show
Series QOMify Sifive UART Model | expand

Commit Message

Lukas Jünger June 13, 2021, 2:12 p.m. UTC
QOMify sifive_uart model

Signed-off-by: Lukas Jünger <lukas.juenger@greensocs.com>
---
 include/hw/char/sifive_uart.h |  11 ++--
 hw/char/sifive_uart.c         | 114 +++++++++++++++++++++++++++++++---
 2 files changed, 109 insertions(+), 16 deletions(-)

Comments

Alistair Francis June 15, 2021, 8:16 a.m. UTC | #1
On Mon, Jun 14, 2021 at 12:20 AM Lukas Jünger
<lukas.juenger@greensocs.com> wrote:
>
> QOMify sifive_uart model
>
> Signed-off-by: Lukas Jünger <lukas.juenger@greensocs.com>

Can you update the titles as requested by Bin?

After that:

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  include/hw/char/sifive_uart.h |  11 ++--
>  hw/char/sifive_uart.c         | 114 +++++++++++++++++++++++++++++++---
>  2 files changed, 109 insertions(+), 16 deletions(-)
>
> diff --git a/include/hw/char/sifive_uart.h b/include/hw/char/sifive_uart.h
> index 3e962be659..7f6c79f8bd 100644
> --- a/include/hw/char/sifive_uart.h
> +++ b/include/hw/char/sifive_uart.h
> @@ -21,6 +21,7 @@
>  #define HW_SIFIVE_UART_H
>
>  #include "chardev/char-fe.h"
> +#include "hw/qdev-properties.h"
>  #include "hw/sysbus.h"
>  #include "qom/object.h"
>
> @@ -49,12 +50,10 @@ enum {
>
>  #define SIFIVE_UART_GET_TXCNT(txctrl)   ((txctrl >> 16) & 0x7)
>  #define SIFIVE_UART_GET_RXCNT(rxctrl)   ((rxctrl >> 16) & 0x7)
> +#define SIFIVE_UART_RX_FIFO_SIZE 8
>
>  #define TYPE_SIFIVE_UART "riscv.sifive.uart"
> -
> -typedef struct SiFiveUARTState SiFiveUARTState;
> -DECLARE_INSTANCE_CHECKER(SiFiveUARTState, SIFIVE_UART,
> -                         TYPE_SIFIVE_UART)
> +OBJECT_DECLARE_SIMPLE_TYPE(SiFiveUARTState, SIFIVE_UART)
>
>  struct SiFiveUARTState {
>      /*< private >*/
> @@ -64,8 +63,8 @@ struct SiFiveUARTState {
>      qemu_irq irq;
>      MemoryRegion mmio;
>      CharBackend chr;
> -    uint8_t rx_fifo[8];
> -    unsigned int rx_fifo_len;
> +    uint8_t rx_fifo[SIFIVE_UART_RX_FIFO_SIZE];
> +    uint8_t rx_fifo_len;
>      uint32_t ie;
>      uint32_t ip;
>      uint32_t txctrl;
> diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
> index 5df8212961..278e21c434 100644
> --- a/hw/char/sifive_uart.c
> +++ b/hw/char/sifive_uart.c
> @@ -19,10 +19,12 @@
>  #include "qemu/osdep.h"
>  #include "qapi/error.h"
>  #include "qemu/log.h"
> +#include "migration/vmstate.h"
>  #include "chardev/char.h"
>  #include "chardev/char-fe.h"
>  #include "hw/irq.h"
>  #include "hw/char/sifive_uart.h"
> +#include "hw/qdev-properties-system.h"
>
>  /*
>   * Not yet implemented:
> @@ -175,20 +177,112 @@ static int sifive_uart_be_change(void *opaque)
>      return 0;
>  }
>
> +static Property sifive_uart_properties[] = {
> +    DEFINE_PROP_CHR("chardev", SiFiveUARTState, chr),
> +    DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void sifive_uart_init(Object *obj)
> +{
> +    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
> +    SiFiveUARTState *s = SIFIVE_UART(obj);
> +
> +    memory_region_init_io(&s->mmio, OBJECT(s), &sifive_uart_ops, s,
> +                          TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
> +    sysbus_init_mmio(sbd, &s->mmio);
> +    sysbus_init_irq(sbd, &s->irq);
> +}
> +
> +static void sifive_uart_realize(DeviceState *dev, Error **errp)
> +{
> +    SiFiveUARTState *s = SIFIVE_UART(dev);
> +
> +    qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx,
> +                             sifive_uart_event, sifive_uart_be_change, s,
> +                             NULL, true);
> +
> +}
> +
> +static void sifive_uart_reset_enter(Object *obj, ResetType type)
> +{
> +    SiFiveUARTState *s = SIFIVE_UART(obj);
> +    s->ie = 0;
> +    s->ip = 0;
> +    s->txctrl = 0;
> +    s->rxctrl = 0;
> +    s->div = 0;
> +    s->rx_fifo_len = 0;
> +}
> +
> +static void sifive_uart_reset_hold(Object *obj)
> +{
> +    SiFiveUARTState *s = SIFIVE_UART(obj);
> +    qemu_irq_lower(s->irq);
> +}
> +
> +static const VMStateDescription vmstate_sifive_uart = {
> +    .name = TYPE_SIFIVE_UART,
> +    .version_id = 1,
> +    .minimum_version_id = 1,
> +    .fields = (VMStateField[]) {
> +        VMSTATE_UINT8_ARRAY(rx_fifo, SiFiveUARTState,
> +                            SIFIVE_UART_RX_FIFO_SIZE),
> +        VMSTATE_UINT8(rx_fifo_len, SiFiveUARTState),
> +        VMSTATE_UINT32(ie, SiFiveUARTState),
> +        VMSTATE_UINT32(ip, SiFiveUARTState),
> +        VMSTATE_UINT32(txctrl, SiFiveUARTState),
> +        VMSTATE_UINT32(rxctrl, SiFiveUARTState),
> +        VMSTATE_UINT32(div, SiFiveUARTState),
> +        VMSTATE_END_OF_LIST()
> +    },
> +};
> +
> +
> +static void sifive_uart_class_init(ObjectClass *oc, void *data)
> +{
> +    DeviceClass *dc = DEVICE_CLASS(oc);
> +    ResettableClass *rc = RESETTABLE_CLASS(oc);
> +
> +    dc->realize = sifive_uart_realize;
> +    dc->vmsd = &vmstate_sifive_uart;
> +    rc->phases.enter = sifive_uart_reset_enter;
> +    rc->phases.hold  = sifive_uart_reset_hold;
> +    device_class_set_props(dc, sifive_uart_properties);
> +}
> +
> +static const TypeInfo sifive_uart_info = {
> +    .name          = TYPE_SIFIVE_UART,
> +    .parent        = TYPE_SYS_BUS_DEVICE,
> +    .instance_size = sizeof(SiFiveUARTState),
> +    .instance_init = sifive_uart_init,
> +    .class_init    = sifive_uart_class_init,
> +};
> +
> +static void sifive_uart_register_types(void)
> +{
> +    type_register_static(&sifive_uart_info);
> +}
> +
> +type_init(sifive_uart_register_types)
> +
>  /*
>   * Create UART device.
>   */
>  SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
>      Chardev *chr, qemu_irq irq)
>  {
> -    SiFiveUARTState *s = g_malloc0(sizeof(SiFiveUARTState));
> -    s->irq = irq;
> -    qemu_chr_fe_init(&s->chr, chr, &error_abort);
> -    qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx,
> -                             sifive_uart_event, sifive_uart_be_change, s,
> -                             NULL, true);
> -    memory_region_init_io(&s->mmio, NULL, &sifive_uart_ops, s,
> -                          TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
> -    memory_region_add_subregion(address_space, base, &s->mmio);
> -    return s;
> +    DeviceState *dev;
> +    SysBusDevice *s;
> +    SiFiveUARTState *r;
> +
> +    dev = qdev_new("riscv.sifive.uart");
> +    s = SYS_BUS_DEVICE(dev);
> +    qdev_prop_set_chr(dev, "chardev", chr);
> +    sysbus_realize_and_unref(s, &error_fatal);
> +    memory_region_add_subregion(address_space, base,
> +                                sysbus_mmio_get_region(s, 0));
> +    sysbus_connect_irq(s, 0, irq);
> +
> +    r = SIFIVE_UART(dev);
> +    return r;
>  }
> --
> 2.31.1
>
>
diff mbox series

Patch

diff --git a/include/hw/char/sifive_uart.h b/include/hw/char/sifive_uart.h
index 3e962be659..7f6c79f8bd 100644
--- a/include/hw/char/sifive_uart.h
+++ b/include/hw/char/sifive_uart.h
@@ -21,6 +21,7 @@ 
 #define HW_SIFIVE_UART_H
 
 #include "chardev/char-fe.h"
+#include "hw/qdev-properties.h"
 #include "hw/sysbus.h"
 #include "qom/object.h"
 
@@ -49,12 +50,10 @@  enum {
 
 #define SIFIVE_UART_GET_TXCNT(txctrl)   ((txctrl >> 16) & 0x7)
 #define SIFIVE_UART_GET_RXCNT(rxctrl)   ((rxctrl >> 16) & 0x7)
+#define SIFIVE_UART_RX_FIFO_SIZE 8
 
 #define TYPE_SIFIVE_UART "riscv.sifive.uart"
-
-typedef struct SiFiveUARTState SiFiveUARTState;
-DECLARE_INSTANCE_CHECKER(SiFiveUARTState, SIFIVE_UART,
-                         TYPE_SIFIVE_UART)
+OBJECT_DECLARE_SIMPLE_TYPE(SiFiveUARTState, SIFIVE_UART)
 
 struct SiFiveUARTState {
     /*< private >*/
@@ -64,8 +63,8 @@  struct SiFiveUARTState {
     qemu_irq irq;
     MemoryRegion mmio;
     CharBackend chr;
-    uint8_t rx_fifo[8];
-    unsigned int rx_fifo_len;
+    uint8_t rx_fifo[SIFIVE_UART_RX_FIFO_SIZE];
+    uint8_t rx_fifo_len;
     uint32_t ie;
     uint32_t ip;
     uint32_t txctrl;
diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
index 5df8212961..278e21c434 100644
--- a/hw/char/sifive_uart.c
+++ b/hw/char/sifive_uart.c
@@ -19,10 +19,12 @@ 
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "qemu/log.h"
+#include "migration/vmstate.h"
 #include "chardev/char.h"
 #include "chardev/char-fe.h"
 #include "hw/irq.h"
 #include "hw/char/sifive_uart.h"
+#include "hw/qdev-properties-system.h"
 
 /*
  * Not yet implemented:
@@ -175,20 +177,112 @@  static int sifive_uart_be_change(void *opaque)
     return 0;
 }
 
+static Property sifive_uart_properties[] = {
+    DEFINE_PROP_CHR("chardev", SiFiveUARTState, chr),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void sifive_uart_init(Object *obj)
+{
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+    SiFiveUARTState *s = SIFIVE_UART(obj);
+
+    memory_region_init_io(&s->mmio, OBJECT(s), &sifive_uart_ops, s,
+                          TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
+    sysbus_init_mmio(sbd, &s->mmio);
+    sysbus_init_irq(sbd, &s->irq);
+}
+
+static void sifive_uart_realize(DeviceState *dev, Error **errp)
+{
+    SiFiveUARTState *s = SIFIVE_UART(dev);
+
+    qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx,
+                             sifive_uart_event, sifive_uart_be_change, s,
+                             NULL, true);
+
+}
+
+static void sifive_uart_reset_enter(Object *obj, ResetType type)
+{
+    SiFiveUARTState *s = SIFIVE_UART(obj);
+    s->ie = 0;
+    s->ip = 0;
+    s->txctrl = 0;
+    s->rxctrl = 0;
+    s->div = 0;
+    s->rx_fifo_len = 0;
+}
+
+static void sifive_uart_reset_hold(Object *obj)
+{
+    SiFiveUARTState *s = SIFIVE_UART(obj);
+    qemu_irq_lower(s->irq);
+}
+
+static const VMStateDescription vmstate_sifive_uart = {
+    .name = TYPE_SIFIVE_UART,
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT8_ARRAY(rx_fifo, SiFiveUARTState,
+                            SIFIVE_UART_RX_FIFO_SIZE),
+        VMSTATE_UINT8(rx_fifo_len, SiFiveUARTState),
+        VMSTATE_UINT32(ie, SiFiveUARTState),
+        VMSTATE_UINT32(ip, SiFiveUARTState),
+        VMSTATE_UINT32(txctrl, SiFiveUARTState),
+        VMSTATE_UINT32(rxctrl, SiFiveUARTState),
+        VMSTATE_UINT32(div, SiFiveUARTState),
+        VMSTATE_END_OF_LIST()
+    },
+};
+
+
+static void sifive_uart_class_init(ObjectClass *oc, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(oc);
+    ResettableClass *rc = RESETTABLE_CLASS(oc);
+
+    dc->realize = sifive_uart_realize;
+    dc->vmsd = &vmstate_sifive_uart;
+    rc->phases.enter = sifive_uart_reset_enter;
+    rc->phases.hold  = sifive_uart_reset_hold;
+    device_class_set_props(dc, sifive_uart_properties);
+}
+
+static const TypeInfo sifive_uart_info = {
+    .name          = TYPE_SIFIVE_UART,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(SiFiveUARTState),
+    .instance_init = sifive_uart_init,
+    .class_init    = sifive_uart_class_init,
+};
+
+static void sifive_uart_register_types(void)
+{
+    type_register_static(&sifive_uart_info);
+}
+
+type_init(sifive_uart_register_types)
+
 /*
  * Create UART device.
  */
 SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
     Chardev *chr, qemu_irq irq)
 {
-    SiFiveUARTState *s = g_malloc0(sizeof(SiFiveUARTState));
-    s->irq = irq;
-    qemu_chr_fe_init(&s->chr, chr, &error_abort);
-    qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx,
-                             sifive_uart_event, sifive_uart_be_change, s,
-                             NULL, true);
-    memory_region_init_io(&s->mmio, NULL, &sifive_uart_ops, s,
-                          TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
-    memory_region_add_subregion(address_space, base, &s->mmio);
-    return s;
+    DeviceState *dev;
+    SysBusDevice *s;
+    SiFiveUARTState *r;
+
+    dev = qdev_new("riscv.sifive.uart");
+    s = SYS_BUS_DEVICE(dev);
+    qdev_prop_set_chr(dev, "chardev", chr);
+    sysbus_realize_and_unref(s, &error_fatal);
+    memory_region_add_subregion(address_space, base,
+                                sysbus_mmio_get_region(s, 0));
+    sysbus_connect_irq(s, 0, irq);
+
+    r = SIFIVE_UART(dev);
+    return r;
 }