| Message ID | 20210617174323.2900831-6-f4bug@amsat.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/mips: Various fixes & cleanups | expand |
On 6/17/21 10:43 AM, Philippe Mathieu-Daudé wrote: > Commit 043715d1e0f ("target/mips: Update ITU to utilize SAARI > and SAAR CP0 registers") declared itc_reconfigure() in public > namespace, while it is restricted to system emulation. > > Similarly commit 5679479b9a1 ("target/mips: Move CP0 helpers > to sysemu/cp0.c") restricted cpu_mips_soft_irq() definition to > system emulation, but forgot to restrict its declaration. > > Commit a2b0a27d33e ("target/mips: Move TCG source files under > tcg/ sub directory") restricted mips_cpu_do_unaligned_access() > to system emulation but forgot to guard the declaration. FWIW, I think the unaligned_access tcg_ops hook should be available for user-only as well, like for tlb_fill. That it is sysemu only at the moment is a bug that affects user-only atomic access. Anyway, Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~ > > To avoid polluting user-mode emulation with these declarations, > restrict them to sysemu. Also restrict the sysemu ITU/ITC/IRQ > fields from CPUMIPSState. > > Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org> > --- > target/mips/cpu.h | 10 +++++++--- > target/mips/tcg/tcg-internal.h | 6 +++--- > 2 files changed, 10 insertions(+), 6 deletions(-)
On 6/19/21 12:38 AM, Richard Henderson wrote: > On 6/17/21 10:43 AM, Philippe Mathieu-Daudé wrote: >> Commit 043715d1e0f ("target/mips: Update ITU to utilize SAARI >> and SAAR CP0 registers") declared itc_reconfigure() in public >> namespace, while it is restricted to system emulation. >> >> Similarly commit 5679479b9a1 ("target/mips: Move CP0 helpers >> to sysemu/cp0.c") restricted cpu_mips_soft_irq() definition to >> system emulation, but forgot to restrict its declaration. >> >> Commit a2b0a27d33e ("target/mips: Move TCG source files under >> tcg/ sub directory") restricted mips_cpu_do_unaligned_access() >> to system emulation but forgot to guard the declaration. > > FWIW, I think the unaligned_access tcg_ops hook should be available for > user-only as well, like for tlb_fill. That it is sysemu only at the > moment is a bug that affects user-only atomic access. OK understood, I'll drop that hunk. > Anyway, > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Thanks!
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 075c24abdad..1dfe69c6c0c 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1152,13 +1152,13 @@ struct CPUMIPSState { CPUMIPSMVPContext *mvp; #if !defined(CONFIG_USER_ONLY) CPUMIPSTLBContext *tlb; + void *irq[8]; + struct MIPSITUState *itu; + MemoryRegion *itc_tag; /* ITC Configuration Tags */ #endif const mips_def_t *cpu_model; - void *irq[8]; QEMUTimer *timer; /* Internal timer */ - struct MIPSITUState *itu; - MemoryRegion *itc_tag; /* ITC Configuration Tags */ target_ulong exception_base; /* ExceptionBase input to the core */ uint64_t cp0_count_ns; /* CP0_Count clock period (in nanoseconds) */ }; @@ -1316,12 +1316,16 @@ uint64_t cpu_mips_phys_to_kseg1(void *opaque, uint64_t addr); bool mips_um_ksegs_enabled(void); void mips_um_ksegs_enable(void); +#if !defined(CONFIG_USER_ONLY) + /* mips_int.c */ void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level); /* mips_itu.c */ void itc_reconfigure(struct MIPSITUState *tag); +#endif /* !CONFIG_USER_ONLY */ + /* helper.c */ target_ulong exception_resume_pc(CPUMIPSState *env); diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index 81b14eb219e..11d98a717f2 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -23,9 +23,6 @@ bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); -void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); const char *mips_exception_name(int32_t exception); @@ -57,6 +54,9 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr); +void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr); void cpu_mips_tlb_flush(CPUMIPSState *env); #endif /* !CONFIG_USER_ONLY */
Commit 043715d1e0f ("target/mips: Update ITU to utilize SAARI and SAAR CP0 registers") declared itc_reconfigure() in public namespace, while it is restricted to system emulation. Similarly commit 5679479b9a1 ("target/mips: Move CP0 helpers to sysemu/cp0.c") restricted cpu_mips_soft_irq() definition to system emulation, but forgot to restrict its declaration. Commit a2b0a27d33e ("target/mips: Move TCG source files under tcg/ sub directory") restricted mips_cpu_do_unaligned_access() to system emulation but forgot to guard the declaration. To avoid polluting user-mode emulation with these declarations, restrict them to sysemu. Also restrict the sysemu ITU/ITC/IRQ fields from CPUMIPSState. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> --- target/mips/cpu.h | 10 +++++++--- target/mips/tcg/tcg-internal.h | 6 +++--- 2 files changed, 10 insertions(+), 6 deletions(-)