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[83.35.24.93]) by smtp.gmail.com with ESMTPSA id e17sm6947404wre.79.2021.06.17.10.49.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Jun 2021 10:49:27 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 4/4] target/mips: Add declarations for generic DSP TCG helpers Date: Thu, 17 Jun 2021 19:49:07 +0200 Message-Id: <20210617174907.2904067-5-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210617174907.2904067-1-f4bug@amsat.org> References: <20210617174907.2904067-1-f4bug@amsat.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x431.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" To be able to extract the DSP ASE translation routines to different source file, declare few TCG helpers, MASK_SPECIAL3 and a DSP register in "translate.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/tcg/translate.h | 7 +++++++ target/mips/tcg/translate.c | 10 +++++----- 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index c25fad597d5..c6f57de7e0d 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -52,6 +52,8 @@ typedef struct DisasContext { /* MIPS major opcodes */ #define MASK_OP_MAJOR(op) (op & (0x3F << 26)) +#define MASK_SPECIAL3(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) + #define OPC_CP1 (0x11 << 26) /* Coprocessor 1 (rs field) */ @@ -131,6 +133,10 @@ void check_cp1_64bitmode(DisasContext *ctx); void check_cp1_registers(DisasContext *ctx, int regs); void check_cop1x(DisasContext *ctx); +void check_dsp(DisasContext *ctx); +void check_dsp_r2(DisasContext *ctx); +void check_dsp_r3(DisasContext *ctx); + void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset); void gen_move_low32(TCGv ret, TCGv_i64 arg); void gen_move_high32(TCGv ret, TCGv_i64 arg); @@ -168,6 +174,7 @@ extern TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; extern TCGv_i32 fpu_fcr0, fpu_fcr31; extern TCGv_i64 fpu_f64[32]; extern TCGv bcond; +extern TCGv cpu_dspctrl; #define LOG_DISAS(...) \ do { \ diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 7b173e2bd2f..97ef816e95f 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -374,7 +374,6 @@ enum { }; /* Special3 opcodes */ -#define MASK_SPECIAL3(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) enum { OPC_EXT = 0x00 | OPC_SPECIAL3, @@ -1227,8 +1226,9 @@ TCGv cpu_gpr[32], cpu_PC; */ TCGv_i64 cpu_gpr_hi[32]; TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; -static TCGv cpu_dspctrl, btarget; +static TCGv btarget; TCGv bcond; +TCGv cpu_dspctrl; static TCGv cpu_lladdr, cpu_llval; static TCGv_i32 hflags; TCGv_i32 fpu_fcr0, fpu_fcr31; @@ -1633,7 +1633,7 @@ void check_cp1_registers(DisasContext *ctx, int regs) * Verify that the processor is running with DSP instructions enabled. * This is enabled by CP0 Status register MX(24) bit. */ -static inline void check_dsp(DisasContext *ctx) +void check_dsp(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP))) { if (ctx->insn_flags & ASE_DSP) { @@ -1644,7 +1644,7 @@ static inline void check_dsp(DisasContext *ctx) } } -static inline void check_dsp_r2(DisasContext *ctx) +void check_dsp_r2(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP_R2))) { if (ctx->insn_flags & ASE_DSP) { @@ -1655,7 +1655,7 @@ static inline void check_dsp_r2(DisasContext *ctx) } } -static inline void check_dsp_r3(DisasContext *ctx) +void check_dsp_r3(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP_R3))) { if (ctx->insn_flags & ASE_DSP) {