From patchwork Thu Jun 24 10:55:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: LIU Zhiwei X-Patchwork-Id: 12341919 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E78EEC48BDF for ; Thu, 24 Jun 2021 11:25:08 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4ADEF6109D for ; Thu, 24 Jun 2021 11:25:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4ADEF6109D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=c-sky.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:56906 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lwNTn-00013l-Ga for qemu-devel@archiver.kernel.org; Thu, 24 Jun 2021 07:25:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44022) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwNC1-0002EF-Ep; Thu, 24 Jun 2021 07:06:45 -0400 Received: from out28-193.mail.aliyun.com ([115.124.28.193]:56955) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwNBy-0003OX-L1; Thu, 24 Jun 2021 07:06:45 -0400 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1115553|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.533591-0.0146714-0.451738; FP=0|0|0|0|0|-1|-1|-1; HT=ay29a033018047212; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=6; RT=6; SR=0; TI=SMTPD_---.KXK1OK7_1624532797; Received: from roman-VirtualBox.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.KXK1OK7_1624532797) by smtp.aliyun-inc.com(10.147.42.197); Thu, 24 Jun 2021 19:06:37 +0800 From: LIU Zhiwei To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 20/37] target/riscv: 8-bit Multiply with 32-bit Add Instructions Date: Thu, 24 Jun 2021 18:55:04 +0800 Message-Id: <20210624105521.3964-21-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210624105521.3964-1-zhiwei_liu@c-sky.com> References: <20210624105521.3964-1-zhiwei_liu@c-sky.com> Received-SPF: none client-ip=115.124.28.193; envelope-from=zhiwei_liu@c-sky.com; helo=out28-193.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Four "signed or unsigned 8 x signed or unsigned 8" with 32-bit addition (32 = 32 + 8x8 + 8x8 + 8x8 + 8x8). Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 4 +++ target/riscv/insn32.decode | 4 +++ target/riscv/insn_trans/trans_rvp.c.inc | 5 +++ target/riscv/packed_helper.c | 44 +++++++++++++++++++++++++ 4 files changed, 57 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 35c8c61b00..a0e3131512 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1326,3 +1326,7 @@ DEF_HELPER_2(clz32, tl, env, tl) DEF_HELPER_2(clo32, tl, env, tl) DEF_HELPER_3(pbsad, tl, env, tl, tl) DEF_HELPER_4(pbsada, tl, env, tl, tl, tl) + +DEF_HELPER_4(smaqa, tl, env, tl, tl, tl) +DEF_HELPER_4(umaqa, tl, env, tl, tl, tl) +DEF_HELPER_4(smaqa_su, tl, env, tl, tl, tl) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index ce8bdee34b..96288370a6 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -929,3 +929,7 @@ clz32 1010111 11001 ..... 000 ..... 1110111 @r2 clo32 1010111 11011 ..... 000 ..... 1110111 @r2 pbsad 1111110 ..... ..... 000 ..... 1110111 @r pbsada 1111111 ..... ..... 000 ..... 1110111 @r + +smaqa 1100100 ..... ..... 000 ..... 1110111 @r +umaqa 1100110 ..... ..... 000 ..... 1110111 @r +smaqa_su 1100101 ..... ..... 000 ..... 1110111 @r diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc index 43e7e5a75d..1a10f13318 100644 --- a/target/riscv/insn_trans/trans_rvp.c.inc +++ b/target/riscv/insn_trans/trans_rvp.c.inc @@ -511,3 +511,8 @@ GEN_RVP_R2_OOL(clz32); GEN_RVP_R2_OOL(clo32); GEN_RVP_R_OOL(pbsad); GEN_RVP_R_ACC_OOL(pbsada); + +/* 8-bit Multiply with 32-bit Add Instructions */ +GEN_RVP_R_ACC_OOL(smaqa); +GEN_RVP_R_ACC_OOL(umaqa); +GEN_RVP_R_ACC_OOL(smaqa_su); diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c index 1f2b90c394..02178d6e61 100644 --- a/target/riscv/packed_helper.c +++ b/target/riscv/packed_helper.c @@ -2044,3 +2044,47 @@ static inline void do_pbsada(CPURISCVState *env, void *vd, void *va, } RVPR_ACC(pbsada, 1, 1); + +/* 8-bit Multiply with 32-bit Add Instructions */ +static inline void do_smaqa(CPURISCVState *env, void *vd, void *va, + void *vb, void *vc, uint8_t i) +{ + int8_t *a = va, *b = vb; + int32_t *d = vd, *c = vc; + + d[H4(i)] = c[H4(i)] + a[H1(i * 4)] * b[H1(i * 4)] + + a[H1(i * 4 + 1)] * b[H1(i * 4 + 1)] + + a[H1(i * 4 + 2)] * b[H1(i * 4 + 2)] + + a[H1(i * 4 + 3)] * b[H1(i * 4 + 3)]; +} + +RVPR_ACC(smaqa, 1, 4); + +static inline void do_umaqa(CPURISCVState *env, void *vd, void *va, + void *vb, void *vc, uint8_t i) +{ + uint8_t *a = va, *b = vb; + uint32_t *d = vd, *c = vc; + + d[H4(i)] = c[H4(i)] + a[H1(i * 4)] * b[H1(i * 4)] + + a[H1(i * 4 + 1)] * b[H1(i * 4 + 1)] + + a[H1(i * 4 + 2)] * b[H1(i * 4 + 2)] + + a[H1(i * 4 + 3)] * b[H1(i * 4 + 3)]; +} + +RVPR_ACC(umaqa, 1, 4); + +static inline void do_smaqa_su(CPURISCVState *env, void *vd, void *va, + void *vb, void *vc, uint8_t i) +{ + int8_t *a = va; + uint8_t *b = vb; + int32_t *d = vd, *c = vc; + + d[H4(i)] = c[H4(i)] + a[H1(i * 4)] * b[H1(i * 4)] + + a[H1(i * 4 + 1)] * b[H1(i * 4 + 1)] + + a[H1(i * 4 + 2)] * b[H1(i * 4 + 2)] + + a[H1(i * 4 + 3)] * b[H1(i * 4 + 3)]; +} + +RVPR_ACC(smaqa_su, 1, 4);