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24 Jun 2021 04:39:31 -0700 IronPort-SDR: RTvru4PtCZ0G7zN/yNbJViUdsJOXiPjVTUKOUSNX7E4PEbkjydyCd5dDLcW8TZSCleVw7PUmsP YWQJ2q7pGh9dDgeUUKzkgX87iygqA+owekXOUlp5G/sUwEanPt3hHdvL8Zxy2G2O5QF2msoPUk dKinStAaQzlnDgbR/aDYB5ZihK973FXUxn/OTN8KLO0DBszHHBkCC0GXHXnWl4e5UYnDVQWk75 jSi9ikmjDjlvXH+yT/C3vlOrR5HZCKItUcGkeX660cAzkYnzCokqY2R8OlMY1DtPjoRh1df6/Y q54= WDCIronportException: Internal Received: from risc6-mainframe.sdcorp.global.sandisk.com (HELO risc6-mainframe.int.fusionio.com) ([10.196.157.248]) by uls-op-cesaip02.wdc.com with ESMTP; 24 Jun 2021 05:02:16 -0700 From: Alistair Francis To: peter.maydell@linaro.org, qemu-devel@nongnu.org Subject: [PULL 3/7] hw/char: Consistent function names for sifive_uart Date: Thu, 24 Jun 2021 05:02:07 -0700 Message-Id: <20210624120211.85499-4-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210624120211.85499-1-alistair.francis@wdc.com> References: <20210624120211.85499-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=802348aeb=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Alistair Francis , =?utf-8?q?Lukas_J=C3=BCnger?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Lukas Jünger This cleans up function names in the SiFive UART model. Signed-off-by: Lukas Jünger Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Message-id: 20210616092326.59639-2-lukas.juenger@greensocs.com Signed-off-by: Alistair Francis --- hw/char/sifive_uart.c | 46 ++++++++++++++++++++++--------------------- 1 file changed, 24 insertions(+), 22 deletions(-) diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c index fe12666789..5df8212961 100644 --- a/hw/char/sifive_uart.c +++ b/hw/char/sifive_uart.c @@ -31,7 +31,7 @@ */ /* Returns the state of the IP (interrupt pending) register */ -static uint64_t uart_ip(SiFiveUARTState *s) +static uint64_t sifive_uart_ip(SiFiveUARTState *s) { uint64_t ret = 0; @@ -48,7 +48,7 @@ static uint64_t uart_ip(SiFiveUARTState *s) return ret; } -static void update_irq(SiFiveUARTState *s) +static void sifive_uart_update_irq(SiFiveUARTState *s) { int cond = 0; if ((s->ie & SIFIVE_UART_IE_TXWM) || @@ -63,7 +63,7 @@ static void update_irq(SiFiveUARTState *s) } static uint64_t -uart_read(void *opaque, hwaddr addr, unsigned int size) +sifive_uart_read(void *opaque, hwaddr addr, unsigned int size) { SiFiveUARTState *s = opaque; unsigned char r; @@ -74,7 +74,7 @@ uart_read(void *opaque, hwaddr addr, unsigned int size) memmove(s->rx_fifo, s->rx_fifo + 1, s->rx_fifo_len - 1); s->rx_fifo_len--; qemu_chr_fe_accept_input(&s->chr); - update_irq(s); + sifive_uart_update_irq(s); return r; } return 0x80000000; @@ -84,7 +84,7 @@ uart_read(void *opaque, hwaddr addr, unsigned int size) case SIFIVE_UART_IE: return s->ie; case SIFIVE_UART_IP: - return uart_ip(s); + return sifive_uart_ip(s); case SIFIVE_UART_TXCTRL: return s->txctrl; case SIFIVE_UART_RXCTRL: @@ -99,8 +99,8 @@ uart_read(void *opaque, hwaddr addr, unsigned int size) } static void -uart_write(void *opaque, hwaddr addr, - uint64_t val64, unsigned int size) +sifive_uart_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) { SiFiveUARTState *s = opaque; uint32_t value = val64; @@ -109,11 +109,11 @@ uart_write(void *opaque, hwaddr addr, switch (addr) { case SIFIVE_UART_TXFIFO: qemu_chr_fe_write(&s->chr, &ch, 1); - update_irq(s); + sifive_uart_update_irq(s); return; case SIFIVE_UART_IE: s->ie = val64; - update_irq(s); + sifive_uart_update_irq(s); return; case SIFIVE_UART_TXCTRL: s->txctrl = val64; @@ -129,9 +129,9 @@ uart_write(void *opaque, hwaddr addr, __func__, (int)addr, (int)value); } -static const MemoryRegionOps uart_ops = { - .read = uart_read, - .write = uart_write, +static const MemoryRegionOps sifive_uart_ops = { + .read = sifive_uart_read, + .write = sifive_uart_write, .endianness = DEVICE_NATIVE_ENDIAN, .valid = { .min_access_size = 4, @@ -139,7 +139,7 @@ static const MemoryRegionOps uart_ops = { } }; -static void uart_rx(void *opaque, const uint8_t *buf, int size) +static void sifive_uart_rx(void *opaque, const uint8_t *buf, int size) { SiFiveUARTState *s = opaque; @@ -150,26 +150,27 @@ static void uart_rx(void *opaque, const uint8_t *buf, int size) } s->rx_fifo[s->rx_fifo_len++] = *buf; - update_irq(s); + sifive_uart_update_irq(s); } -static int uart_can_rx(void *opaque) +static int sifive_uart_can_rx(void *opaque) { SiFiveUARTState *s = opaque; return s->rx_fifo_len < sizeof(s->rx_fifo); } -static void uart_event(void *opaque, QEMUChrEvent event) +static void sifive_uart_event(void *opaque, QEMUChrEvent event) { } -static int uart_be_change(void *opaque) +static int sifive_uart_be_change(void *opaque) { SiFiveUARTState *s = opaque; - qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event, - uart_be_change, s, NULL, true); + qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx, + sifive_uart_event, sifive_uart_be_change, s, + NULL, true); return 0; } @@ -183,9 +184,10 @@ SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base, SiFiveUARTState *s = g_malloc0(sizeof(SiFiveUARTState)); s->irq = irq; qemu_chr_fe_init(&s->chr, chr, &error_abort); - qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event, - uart_be_change, s, NULL, true); - memory_region_init_io(&s->mmio, NULL, &uart_ops, s, + qemu_chr_fe_set_handlers(&s->chr, sifive_uart_can_rx, sifive_uart_rx, + sifive_uart_event, sifive_uart_be_change, s, + NULL, true); + memory_region_init_io(&s->mmio, NULL, &sifive_uart_ops, s, TYPE_SIFIVE_UART, SIFIVE_UART_MAX); memory_region_add_subregion(address_space, base, &s->mmio); return s;