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12 Jul 2021 15:31:58 -0700 IronPort-SDR: 74UlS8yJ3f7uIZgG0+GuaSnZlOnTPKhR63xVxijGeuRbLzXLVY7ggGCGeSMgJ6pVvq2BHP1n3j QClmuQA2gqtvrb5UE/AqHtKy+u6SGB+6n2YxF7bk/ZKwngqrKNtAkJzxqkiJaXcHBJbz3UE2C/ EXqmTmUrEs59za3lZF5RmOKbooCgHzN0d+qlkE8KewrSdLAt8Z9npR38v1jiSL4mxZj5hmem/s SsGFKwzIGQyGrBlN0RS4qETtosM+6Bzj48rRpJ8sT3FMOQJqCnPKavc65wjKQa/gET7PUbH7oR gWU= WDCIronportException: Internal Received: from risc6-mainframe.sdcorp.global.sandisk.com (HELO risc6-mainframe.int.fusionio.com) ([10.196.157.248]) by uls-op-cesaip01.wdc.com with ESMTP; 12 Jul 2021 15:53:52 -0700 From: Alistair Francis To: peter.maydell@linaro.org, qemu-devel@nongnu.org Subject: [PULL 05/11] target/riscv: hardwire bits in hideleg and hedeleg Date: Mon, 12 Jul 2021 15:53:42 -0700 Message-Id: <20210712225348.213819-6-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210712225348.213819-1-alistair.francis@wdc.com> References: <20210712225348.213819-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=820a0e1fd=alistair.francis@wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jose Martins , Alistair Francis , LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Jose Martins The specification mandates for certain bits to be hardwired in the hypervisor delegation registers. This was not being enforced. Signed-off-by: Jose Martins Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Message-id: 20210522155902.374439-1-josemartins90@gmail.com [ Changes by AF: - Improve indentation ] Signed-off-by: Alistair Francis --- target/riscv/csr.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 62b968326c..b904d2bcb0 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -411,6 +411,7 @@ static RISCVException read_timeh(CPURISCVState *env, int csrno, static const target_ulong delegable_ints = S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS; +static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS; static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS; static const target_ulong delegable_excps = @@ -433,6 +434,14 @@ static const target_ulong delegable_excps = (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)); +static const target_ulong vs_delegable_excps = delegable_excps & + ~((1ULL << (RISCV_EXCP_S_ECALL)) | + (1ULL << (RISCV_EXCP_VS_ECALL)) | + (1ULL << (RISCV_EXCP_M_ECALL)) | + (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | + (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | + (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | + (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT))); static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS | SSTATUS_SUM | SSTATUS_MXR; @@ -1039,7 +1048,7 @@ static RISCVException read_hedeleg(CPURISCVState *env, int csrno, static RISCVException write_hedeleg(CPURISCVState *env, int csrno, target_ulong val) { - env->hedeleg = val; + env->hedeleg = val & vs_delegable_excps; return RISCV_EXCP_NONE; } @@ -1053,7 +1062,7 @@ static RISCVException read_hideleg(CPURISCVState *env, int csrno, static RISCVException write_hideleg(CPURISCVState *env, int csrno, target_ulong val) { - env->hideleg = val; + env->hideleg = val & vs_delegable_ints; return RISCV_EXCP_NONE; }