| Message ID | 20210713004205.775386-2-jusual@redhat.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Use ACPI PCI hot-plug for Q35 | expand |
On Tue, Jul 13, 2021 at 02:42:00AM +0200, Julia Suvorova wrote: > Implement notifications and gpe to support q35 ACPI PCI hot-plug. > Use 0xcc4 - 0xcd7 range for 'acpi-pci-hotplug' io ports. > > Signed-off-by: Julia Suvorova <jusual@redhat.com> > Reviewed-by: Igor Mammedov <imammedo@redhat.com> > Reviewed-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> I'm not especially familiar with either x86 or ACPI code, so my review's depth is according. > --- > hw/i386/acpi-build.h | 4 ++++ > include/hw/acpi/ich9.h | 2 ++ > include/hw/acpi/pcihp.h | 3 ++- > hw/acpi/pcihp.c | 6 +++--- > hw/acpi/piix4.c | 4 +++- > hw/i386/acpi-build.c | 30 +++++++++++++++++++----------- > 6 files changed, 33 insertions(+), 16 deletions(-) > > diff --git a/hw/i386/acpi-build.h b/hw/i386/acpi-build.h > index 74df5fc612..487ec7710f 100644 > --- a/hw/i386/acpi-build.h > +++ b/hw/i386/acpi-build.h > @@ -5,6 +5,10 @@ > > extern const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio; > > +/* PCI Hot-plug registers bases. See docs/spec/acpi_pci_hotplug.txt */ > +#define ACPI_PCIHP_SEJ_BASE 0x8 > +#define ACPI_PCIHP_BNMR_BASE 0x10 > + > void acpi_setup(void); > > #endif > diff --git a/include/hw/acpi/ich9.h b/include/hw/acpi/ich9.h > index df519e40b5..596120d97f 100644 > --- a/include/hw/acpi/ich9.h > +++ b/include/hw/acpi/ich9.h > @@ -28,6 +28,8 @@ > #include "hw/acpi/acpi_dev_interface.h" > #include "hw/acpi/tco.h" > > +#define ACPI_PCIHP_ADDR_ICH9 0x0cc4 > + > typedef struct ICH9LPCPMRegs { > /* > * In ich9 spec says that pm1_cnt register is 32bit width and > diff --git a/include/hw/acpi/pcihp.h b/include/hw/acpi/pcihp.h > index 2dd90aea30..af1a169fc3 100644 > --- a/include/hw/acpi/pcihp.h > +++ b/include/hw/acpi/pcihp.h > @@ -55,7 +55,8 @@ typedef struct AcpiPciHpState { > } AcpiPciHpState; > > void acpi_pcihp_init(Object *owner, AcpiPciHpState *, PCIBus *root, > - MemoryRegion *address_space_io, bool bridges_enabled); > + MemoryRegion *address_space_io, bool bridges_enabled, > + uint16_t io_base); > > void acpi_pcihp_device_pre_plug_cb(HotplugHandler *hotplug_dev, > DeviceState *dev, Error **errp); > diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c > index 4999277d57..d98a284b7a 100644 > --- a/hw/acpi/pcihp.c > +++ b/hw/acpi/pcihp.c > @@ -37,7 +37,6 @@ > #include "qom/qom-qobject.h" > #include "trace.h" > > -#define ACPI_PCIHP_ADDR 0xae00 > #define ACPI_PCIHP_SIZE 0x0018 > #define PCI_UP_BASE 0x0000 > #define PCI_DOWN_BASE 0x0004 > @@ -488,10 +487,11 @@ static const MemoryRegionOps acpi_pcihp_io_ops = { > }; > > void acpi_pcihp_init(Object *owner, AcpiPciHpState *s, PCIBus *root_bus, > - MemoryRegion *address_space_io, bool bridges_enabled) > + MemoryRegion *address_space_io, bool bridges_enabled, > + uint16_t io_base) > { > s->io_len = ACPI_PCIHP_SIZE; > - s->io_base = ACPI_PCIHP_ADDR; > + s->io_base = io_base; > > s->root = root_bus; > s->legacy_piix = !bridges_enabled; > diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c > index 0bd23d74e2..48f7a1edbc 100644 > --- a/hw/acpi/piix4.c > +++ b/hw/acpi/piix4.c > @@ -49,6 +49,8 @@ > #define GPE_BASE 0xafe0 > #define GPE_LEN 4 > > +#define ACPI_PCIHP_ADDR_PIIX4 0xae00 > + > struct pci_status { > uint32_t up; /* deprecated, maintained for migration compatibility */ > uint32_t down; > @@ -607,7 +609,7 @@ static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, > > if (s->use_acpi_hotplug_bridge || s->use_acpi_root_pci_hotplug) { > acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent, > - s->use_acpi_hotplug_bridge); > + s->use_acpi_hotplug_bridge, ACPI_PCIHP_ADDR_PIIX4); > } > > s->cpu_hotplug_legacy = true; > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c > index 357437ff1d..e1c246d6e8 100644 > --- a/hw/i386/acpi-build.c > +++ b/hw/i386/acpi-build.c > @@ -219,10 +219,6 @@ static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) > /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ > pm->fadt.rev = 1; > pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; > - pm->pcihp_io_base = > - object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); > - pm->pcihp_io_len = > - object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); > } > if (lpc) { > uint64_t smi_features = object_property_get_uint(lpc, > @@ -238,6 +234,10 @@ static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) > pm->smi_on_cpu_unplug = > !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)); > } > + pm->pcihp_io_base = > + object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); > + pm->pcihp_io_len = > + object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); > > /* The above need not be conditional on machine type because the reset port > * happens to be the same on PIIX (pc) and ICH9 (q35). */ > @@ -392,6 +392,9 @@ static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, > > if (!pdev) { > if (bsel) { /* add hotplug slots for non present devices */ > + if (pci_bus_is_express(bus) && slot > 0) { > + break; > + } > dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); > aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); > aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); > @@ -521,7 +524,7 @@ static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, > QLIST_FOREACH(sec, &bus->child, sibling) { > int32_t devfn = sec->parent_dev->devfn; > > - if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) { > + if (pci_bus_is_root(sec)) { > continue; > } > > @@ -1251,7 +1254,7 @@ static void build_piix4_isa_bridge(Aml *table) > aml_append(table, scope); > } > > -static void build_piix4_pci_hotplug(Aml *table) > +static void build_x86_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr) > { > Aml *scope; > Aml *field; > @@ -1260,20 +1263,22 @@ static void build_piix4_pci_hotplug(Aml *table) > scope = aml_scope("_SB.PCI0"); > > aml_append(scope, > - aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08)); > + aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0x08)); > field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); > aml_append(field, aml_named_field("PCIU", 32)); > aml_append(field, aml_named_field("PCID", 32)); > aml_append(scope, field); > > aml_append(scope, > - aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04)); > + aml_operation_region("SEJ", AML_SYSTEM_IO, > + aml_int(pcihp_addr + ACPI_PCIHP_SEJ_BASE), 0x04)); > field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); > aml_append(field, aml_named_field("B0EJ", 32)); > aml_append(scope, field); > > aml_append(scope, > - aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x08)); > + aml_operation_region("BNMR", AML_SYSTEM_IO, > + aml_int(pcihp_addr + ACPI_PCIHP_BNMR_BASE), 0x08)); > field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); > aml_append(field, aml_named_field("BNUM", 32)); > aml_append(field, aml_named_field("PIDX", 32)); > @@ -1407,7 +1412,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > build_piix4_isa_bridge(dsdt); > build_isa_devices_aml(dsdt); > if (pm->pcihp_bridge_en || pm->pcihp_root_en) { > - build_piix4_pci_hotplug(dsdt); > + build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); > } > build_piix4_pci0_int(dsdt); > } else { > @@ -1455,6 +1460,9 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > } > build_q35_isa_bridge(dsdt); > build_isa_devices_aml(dsdt); > + if (pm->pcihp_bridge_en) { > + build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); > + } > build_q35_pci0_int(dsdt); > if (pcms->smbus && !pcmc->do_not_add_smb_acpi) { > build_smb0(dsdt, pcms->smbus, ICH9_SMB_DEV, ICH9_SMB_FUNC); > @@ -1489,7 +1497,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > { > aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); > > - if (misc->is_piix4 && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { > + if (pm->pcihp_bridge_en || pm->pcihp_root_en) { > method = aml_method("_E01", 0, AML_NOTSERIALIZED); > aml_append(method, > aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
diff --git a/hw/i386/acpi-build.h b/hw/i386/acpi-build.h index 74df5fc612..487ec7710f 100644 --- a/hw/i386/acpi-build.h +++ b/hw/i386/acpi-build.h @@ -5,6 +5,10 @@ extern const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio; +/* PCI Hot-plug registers bases. See docs/spec/acpi_pci_hotplug.txt */ +#define ACPI_PCIHP_SEJ_BASE 0x8 +#define ACPI_PCIHP_BNMR_BASE 0x10 + void acpi_setup(void); #endif diff --git a/include/hw/acpi/ich9.h b/include/hw/acpi/ich9.h index df519e40b5..596120d97f 100644 --- a/include/hw/acpi/ich9.h +++ b/include/hw/acpi/ich9.h @@ -28,6 +28,8 @@ #include "hw/acpi/acpi_dev_interface.h" #include "hw/acpi/tco.h" +#define ACPI_PCIHP_ADDR_ICH9 0x0cc4 + typedef struct ICH9LPCPMRegs { /* * In ich9 spec says that pm1_cnt register is 32bit width and diff --git a/include/hw/acpi/pcihp.h b/include/hw/acpi/pcihp.h index 2dd90aea30..af1a169fc3 100644 --- a/include/hw/acpi/pcihp.h +++ b/include/hw/acpi/pcihp.h @@ -55,7 +55,8 @@ typedef struct AcpiPciHpState { } AcpiPciHpState; void acpi_pcihp_init(Object *owner, AcpiPciHpState *, PCIBus *root, - MemoryRegion *address_space_io, bool bridges_enabled); + MemoryRegion *address_space_io, bool bridges_enabled, + uint16_t io_base); void acpi_pcihp_device_pre_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp); diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c index 4999277d57..d98a284b7a 100644 --- a/hw/acpi/pcihp.c +++ b/hw/acpi/pcihp.c @@ -37,7 +37,6 @@ #include "qom/qom-qobject.h" #include "trace.h" -#define ACPI_PCIHP_ADDR 0xae00 #define ACPI_PCIHP_SIZE 0x0018 #define PCI_UP_BASE 0x0000 #define PCI_DOWN_BASE 0x0004 @@ -488,10 +487,11 @@ static const MemoryRegionOps acpi_pcihp_io_ops = { }; void acpi_pcihp_init(Object *owner, AcpiPciHpState *s, PCIBus *root_bus, - MemoryRegion *address_space_io, bool bridges_enabled) + MemoryRegion *address_space_io, bool bridges_enabled, + uint16_t io_base) { s->io_len = ACPI_PCIHP_SIZE; - s->io_base = ACPI_PCIHP_ADDR; + s->io_base = io_base; s->root = root_bus; s->legacy_piix = !bridges_enabled; diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 0bd23d74e2..48f7a1edbc 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -49,6 +49,8 @@ #define GPE_BASE 0xafe0 #define GPE_LEN 4 +#define ACPI_PCIHP_ADDR_PIIX4 0xae00 + struct pci_status { uint32_t up; /* deprecated, maintained for migration compatibility */ uint32_t down; @@ -607,7 +609,7 @@ static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, if (s->use_acpi_hotplug_bridge || s->use_acpi_root_pci_hotplug) { acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent, - s->use_acpi_hotplug_bridge); + s->use_acpi_hotplug_bridge, ACPI_PCIHP_ADDR_PIIX4); } s->cpu_hotplug_legacy = true; diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 357437ff1d..e1c246d6e8 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -219,10 +219,6 @@ static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) /* w2k requires FADT(rev1) or it won't boot, keep PC compatible */ pm->fadt.rev = 1; pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE; - pm->pcihp_io_base = - object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); - pm->pcihp_io_len = - object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); } if (lpc) { uint64_t smi_features = object_property_get_uint(lpc, @@ -238,6 +234,10 @@ static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) pm->smi_on_cpu_unplug = !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)); } + pm->pcihp_io_base = + object_property_get_uint(obj, ACPI_PCIHP_IO_BASE_PROP, NULL); + pm->pcihp_io_len = + object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); /* The above need not be conditional on machine type because the reset port * happens to be the same on PIIX (pc) and ICH9 (q35). */ @@ -392,6 +392,9 @@ static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, if (!pdev) { if (bsel) { /* add hotplug slots for non present devices */ + if (pci_bus_is_express(bus) && slot > 0) { + break; + } dev = aml_device("S%.02X", PCI_DEVFN(slot, 0)); aml_append(dev, aml_name_decl("_SUN", aml_int(slot))); aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16))); @@ -521,7 +524,7 @@ static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, QLIST_FOREACH(sec, &bus->child, sibling) { int32_t devfn = sec->parent_dev->devfn; - if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) { + if (pci_bus_is_root(sec)) { continue; } @@ -1251,7 +1254,7 @@ static void build_piix4_isa_bridge(Aml *table) aml_append(table, scope); } -static void build_piix4_pci_hotplug(Aml *table) +static void build_x86_acpi_pci_hotplug(Aml *table, uint64_t pcihp_addr) { Aml *scope; Aml *field; @@ -1260,20 +1263,22 @@ static void build_piix4_pci_hotplug(Aml *table) scope = aml_scope("_SB.PCI0"); aml_append(scope, - aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08)); + aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(pcihp_addr), 0x08)); field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); aml_append(field, aml_named_field("PCIU", 32)); aml_append(field, aml_named_field("PCID", 32)); aml_append(scope, field); aml_append(scope, - aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04)); + aml_operation_region("SEJ", AML_SYSTEM_IO, + aml_int(pcihp_addr + ACPI_PCIHP_SEJ_BASE), 0x04)); field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); aml_append(field, aml_named_field("B0EJ", 32)); aml_append(scope, field); aml_append(scope, - aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x08)); + aml_operation_region("BNMR", AML_SYSTEM_IO, + aml_int(pcihp_addr + ACPI_PCIHP_BNMR_BASE), 0x08)); field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS); aml_append(field, aml_named_field("BNUM", 32)); aml_append(field, aml_named_field("PIDX", 32)); @@ -1407,7 +1412,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, build_piix4_isa_bridge(dsdt); build_isa_devices_aml(dsdt); if (pm->pcihp_bridge_en || pm->pcihp_root_en) { - build_piix4_pci_hotplug(dsdt); + build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); } build_piix4_pci0_int(dsdt); } else { @@ -1455,6 +1460,9 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, } build_q35_isa_bridge(dsdt); build_isa_devices_aml(dsdt); + if (pm->pcihp_bridge_en) { + build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base); + } build_q35_pci0_int(dsdt); if (pcms->smbus && !pcmc->do_not_add_smb_acpi) { build_smb0(dsdt, pcms->smbus, ICH9_SMB_DEV, ICH9_SMB_FUNC); @@ -1489,7 +1497,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, { aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); - if (misc->is_piix4 && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { + if (pm->pcihp_bridge_en || pm->pcihp_root_en) { method = aml_method("_E01", 0, AML_NOTSERIALIZED); aml_append(method, aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));