From patchwork Tue Jul 20 12:30:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alessandro Di Federico X-Patchwork-Id: 12388171 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66ECFC636C8 for ; Tue, 20 Jul 2021 12:36:19 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 176E96113C for ; Tue, 20 Jul 2021 12:36:19 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 176E96113C Authentication-Results: mail.kernel.org; dmarc=pass (p=none dis=none) header.from=nongnu.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:36202 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m5oyv-0004Xc-Se for qemu-devel@archiver.kernel.org; Tue, 20 Jul 2021 08:36:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46320) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m5otl-0004Vv-AZ for qemu-devel@nongnu.org; Tue, 20 Jul 2021 08:30:57 -0400 Received: from rev.ng ([5.9.113.41]:59983) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m5oth-0004ei-7m for qemu-devel@nongnu.org; Tue, 20 Jul 2021 08:30:56 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=g7K7ah7dzgA9qNNeIHcq61tdQ4zff5490T//67zBwbg=; b=O06w+rw40cd6NYuiXpsdKIo4n7 q3Vpu7jEzzrpEzyWJBiTGbjQgyTZOxec/sz6gSSU7IWq/CGdE9ayRZ7n1b3GQqAO+D3IC9mh2g4Kw Ll8yqR2m8lFnisciAtaof3oTaOu0UK49/XYiNC4kFF8X6xSiPQ98wyFKv1BR4w6uUDPY=; To: qemu-devel@nongnu.org Cc: tsimpson@quicinc.com, bcain@quicinc.com, babush@rev.ng, nizzo@rev.ng, richard.henderson@linaro.org, Alessandro Di Federico Subject: [PATCH v6 03/12] target/hexagon: make slot number an unsigned Date: Tue, 20 Jul 2021 14:30:22 +0200 Message-Id: <20210720123031.1101682-4-ale.qemu@rev.ng> In-Reply-To: <20210720123031.1101682-1-ale.qemu@rev.ng> References: <20210720123031.1101682-1-ale.qemu@rev.ng> MIME-Version: 1.0 Received-SPF: pass client-ip=5.9.113.41; envelope-from=ale@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alessandro Di Federico X-Patchwork-Original-From: Alessandro Di Federico via From: Alessandro Di Federico From: Paolo Montesel Signed-off-by: Alessandro Di Federico Signed-off-by: Paolo Montesel Acked-by: Richard Henderson --- target/hexagon/macros.h | 2 +- target/hexagon/genptr.c | 24 +++++++++++++----------- 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index 094b8dabb5..cd4f878fcf 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -185,7 +185,7 @@ #define LOAD_CANCEL(EA) do { CANCEL; } while (0) #ifdef QEMU_GENERATE -static inline void gen_pred_cancel(TCGv pred, int slot_num) +static inline void gen_pred_cancel(TCGv pred, uint32_t slot_num) { TCGv slot_mask = tcg_const_tl(1 << slot_num); TCGv tmp = tcg_temp_new(); diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 7333299615..2c7f4136b5 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -27,7 +27,8 @@ #undef QEMU_GENERATE #include "gen_tcg.h" -static inline void gen_log_predicated_reg_write(int rnum, TCGv val, int slot) +static inline void gen_log_predicated_reg_write(int rnum, TCGv val, + uint32_t slot) { TCGv zero = tcg_const_tl(0); TCGv slot_mask = tcg_temp_new(); @@ -60,7 +61,8 @@ static inline void gen_log_reg_write(int rnum, TCGv val) } } -static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val, int slot) +static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val, + uint32_t slot) { TCGv val32 = tcg_temp_new(); TCGv zero = tcg_const_tl(0); @@ -379,7 +381,7 @@ static inline void gen_store_conditional8(DisasContext *ctx, tcg_gen_movi_tl(hex_llsc_addr, ~0); } -static inline void gen_store32(TCGv vaddr, TCGv src, int width, int slot) +static inline void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot) { tcg_gen_mov_tl(hex_store_addr[slot], vaddr); tcg_gen_movi_tl(hex_store_width[slot], width); @@ -387,14 +389,14 @@ static inline void gen_store32(TCGv vaddr, TCGv src, int width, int slot) } static inline void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, - DisasContext *ctx, int slot) + DisasContext *ctx, uint32_t slot) { gen_store32(vaddr, src, 1, slot); ctx->store_width[slot] = 1; } static inline void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, - DisasContext *ctx, int slot) + DisasContext *ctx, uint32_t slot) { TCGv tmp = tcg_const_tl(src); gen_store1(cpu_env, vaddr, tmp, ctx, slot); @@ -402,14 +404,14 @@ static inline void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, } static inline void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, - DisasContext *ctx, int slot) + DisasContext *ctx, uint32_t slot) { gen_store32(vaddr, src, 2, slot); ctx->store_width[slot] = 2; } static inline void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, - DisasContext *ctx, int slot) + DisasContext *ctx, uint32_t slot) { TCGv tmp = tcg_const_tl(src); gen_store2(cpu_env, vaddr, tmp, ctx, slot); @@ -417,14 +419,14 @@ static inline void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, } static inline void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, - DisasContext *ctx, int slot) + DisasContext *ctx, uint32_t slot) { gen_store32(vaddr, src, 4, slot); ctx->store_width[slot] = 4; } static inline void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, - DisasContext *ctx, int slot) + DisasContext *ctx, uint32_t slot) { TCGv tmp = tcg_const_tl(src); gen_store4(cpu_env, vaddr, tmp, ctx, slot); @@ -432,7 +434,7 @@ static inline void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, } static inline void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, - DisasContext *ctx, int slot) + DisasContext *ctx, uint32_t slot) { tcg_gen_mov_tl(hex_store_addr[slot], vaddr); tcg_gen_movi_tl(hex_store_width[slot], 8); @@ -441,7 +443,7 @@ static inline void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, } static inline void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, - DisasContext *ctx, int slot) + DisasContext *ctx, uint32_t slot) { TCGv_i64 tmp = tcg_const_i64(src); gen_store8(cpu_env, vaddr, tmp, ctx, slot);