[v2,2/3] target-arm: cpu64: Add support for Fujitsu A64FX

Commit Message

[e-mail] July 30, 2021, 3:08 a.m. UTC

Remove unused definitions, change of appearance and fix for patch consistency
https://lists.gnu.org/archive/html/qemu-devel/2021-07/msg04789.html
https://lists.gnu.org/archive/html/qemu-devel/2021-07/msg04790.html

Signed-off-by: Shuuichirou Ishii <[e-mail]>
---
 docs/system/arm/virt.rst | 1 -
 hw/arm/virt.c            | 1 -
 target/arm/cpu64.c       | 9 +++------
 3 files changed, 3 insertions(+), 8 deletions(-)

Patch

diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
index 5329e952cf..27652adfae 100644
--- a/docs/system/arm/virt.rst
+++ b/docs/system/arm/virt.rst
@@ -55,7 +55,6 @@  Supported guest CPU types:
 - ``cortex-a53`` (64-bit)
 - ``cortex-a57`` (64-bit)
 - ``cortex-a72`` (64-bit)
-- ``a64fx`` (64-bit)
 - ``host`` (with KVM only)
 - ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
 
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 3b8a26a420..81eda46b0b 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -202,7 +202,6 @@  static const char *valid_cpus[] = {
     ARM_CPU_TYPE_NAME("cortex-a72"),
     ARM_CPU_TYPE_NAME("host"),
     ARM_CPU_TYPE_NAME("max"),
-    ARM_CPU_TYPE_NAME("a64fx"),
 };
 
 static bool cpu_type_valid(const char *cpu)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index dd72300e88..2b66e30133 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -847,10 +847,6 @@  static void aarch64_max_initfn(Object *obj)
                         cpu_max_set_sve_max_vq, NULL, NULL);
 }
 
-static const ARMCPRegInfo a64fx_cp_reginfo[] = {
-    /* TODO  Add A64FX specific HPC extensinos registers */
-    REGINFO_SENTINEL
-};
 static void aarch64_a64fx_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
@@ -887,19 +883,20 @@  static void aarch64_a64fx_initfn(Object *obj)
     cpu->gic_num_lrs = 4;
     cpu->gic_vpribits = 5;
     cpu->gic_vprebits = 5;
-    define_arm_cp_regs(cpu, a64fx_cp_reginfo);
+    /* TODO:  Add A64FX specific HPC extension registers */
 
     aarch64_add_sve_properties(obj);
     object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
                         cpu_max_set_sve_max_vq, NULL, NULL);
+
 }
 
 static const ARMCPUInfo aarch64_cpus[] = {
     { .name = "cortex-a57",         .initfn = aarch64_a57_initfn },
     { .name = "cortex-a53",         .initfn = aarch64_a53_initfn },
     { .name = "cortex-a72",         .initfn = aarch64_a72_initfn },
-    { .name = "max",                .initfn = aarch64_max_initfn },
     { .name = "a64fx",              .initfn = aarch64_a64fx_initfn },
+    { .name = "max",                .initfn = aarch64_max_initfn },
 };
 
 static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp)