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Tue, 3 Aug 2021 19:54:07 +0000 (GMT) Received: from vm.lan (unknown [9.145.77.113]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 3 Aug 2021 19:54:07 +0000 (GMT) From: Ilya Leoshkevich To: Riku Voipio , Richard Henderson , Paolo Bonzini Subject: [PATCH] accel/tcg/user-exec: Fix read-modify-write of code on s390 hosts Date: Tue, 3 Aug 2021 21:54:06 +0200 Message-Id: <20210803195406.149446-1-iii@linux.ibm.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: yOj-M-feXQyPEk2vdBMftZ8vWrYEINRk X-Proofpoint-GUID: 1CEKD8pKxepKtJrfilhA7PneipQIGWgZ X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-03_05:2021-08-03, 2021-08-03 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 bulkscore=0 mlxscore=0 spamscore=0 lowpriorityscore=0 clxscore=1011 mlxlogscore=999 impostorscore=0 suspectscore=0 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108030124 Received-SPF: pass client-ip=148.163.158.5; envelope-from=iii@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Christian Borntraeger , qemu-devel@nongnu.org, Ilya Leoshkevich , Andreas Krebbel Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" x86_64 dotnet/runtime uses cmpxchg for code patching. When running it under s390x qemu-linux user, cpu_signal_handler() does not recognize this as a write and does not restore PAGE_WRITE cleared by tb_page_add(), incorrectly forwarding the signal to the guest code. Signed-off-by: Ilya Leoshkevich --- accel/tcg/user-exec.c | 37 ++++++++++++++++++++++++++++++++----- 1 file changed, 32 insertions(+), 5 deletions(-) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 90d1a2d327..587a0f1ef9 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -681,17 +681,24 @@ int cpu_signal_handler(int host_signum, void *pinfo, pc = uc->uc_mcontext.psw.addr; /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead - of the normal 2 arguments. The 3rd argument contains the "int_code" - from the hardware which does in fact contain the is_write value. + of the normal 2 arguments. The 4th argument contains the "Translation- + Exception Identification for DAT Exceptions" from the hardware (aka + "int_parm_long"), which does in fact contain the is_write value. The rt signal handler, as far as I can tell, does not give this value - at all. Not that we could get to it from here even if it were. */ - /* ??? This is not even close to complete, since it ignores all - of the read-modify-write instructions. */ + at all. Not that we could get to it from here even if it were. + So fall back to parsing instructions. Treat read-modify-write ones as + writes, which is not fully correct, but for tracking self-modifying code + this is better than treating them as reads. Checking si_addr page flags + might be a viable improvement, albeit a racy one. */ + /* ??? This is not even close to complete. */ pinsn = (uint16_t *)pc; switch (pinsn[0] >> 8) { case 0x50: /* ST */ case 0x42: /* STC */ case 0x40: /* STH */ + case 0xba: /* CS */ + case 0xbb: /* CDS */ + case 0xc8: /* CSST */ is_write = 1; break; case 0xc4: /* RIL format insns */ @@ -715,7 +722,27 @@ int cpu_signal_handler(int host_signum, void *pinfo, is_write = 1; } break; + case 0xeb: /* RSY format insns */ + switch (pinsn[2] & 0xff) { + case 0x14: /* CSY */ + case 0x30: /* CSG */ + case 0x31: /* CDSY */ + case 0x3e: /* CDSG */ + case 0xe4: /* LANG */ + case 0xe6: /* LAOG */ + case 0xe7: /* LAXG */ + case 0xe8: /* LAAG */ + case 0xea: /* LAALG */ + case 0xf4: /* LAN */ + case 0xf6: /* LAO */ + case 0xf7: /* LAX */ + case 0xfa: /* LAAL */ + case 0xf8: /* LAA */ + is_write = 1; + } + break; } + return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); }