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Mon, 9 Aug 2021 13:46:03 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av22.portsmouth.uk.ibm.com (Postfix) with SMTP; Mon, 9 Aug 2021 13:46:03 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.54.114]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 2C3A322016C; Mon, 9 Aug 2021 15:46:03 +0200 (CEST) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: David Gibson , Greg Kurz Subject: [PATCH 21/26] pnv/xive2: Introduce new capability bits Date: Mon, 9 Aug 2021 15:45:42 +0200 Message-Id: <20210809134547.689560-22-clg@kaod.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210809134547.689560-1-clg@kaod.org> References: <20210809134547.689560-1-clg@kaod.org> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: uY7dVBIoiEEbPGMIGY8LL23Rh1yrS0tK X-Proofpoint-ORIG-GUID: uY7dVBIoiEEbPGMIGY8LL23Rh1yrS0tK X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-08-09_04:2021-08-06, 2021-08-09 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1034 phishscore=0 mlxlogscore=999 adultscore=0 lowpriorityscore=0 impostorscore=0 mlxscore=0 spamscore=0 malwarescore=0 suspectscore=0 priorityscore=1501 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2108090101 Received-SPF: softfail client-ip=148.163.158.5; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -7 X-Spam_score: -0.8 X-Spam_bar: / X-Spam_report: (-0.8 / 5.0 requ) BAYES_00=-1.9, KHOP_HELO_FCRDNS=0.398, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, =?utf-8?q?C=C3=A9dric_Le_Goa?= =?utf-8?q?ter?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" These bits control the availability of interrupt features : StoreEOI, PHB PQ_disable, PHB Address-Based Trigger and the overall XIVE exploitation mode. These bits can be set at early boot time of the system to activate/deactivate a feature for testing purposes. The default value should be '1'. The 'XIVE exploitation mode' bit is a software bit that skiboot could use to disable the XIVE OS interface and propose a P8 style XICS interface instead. There are no plans for that for the moment. Signed-off-by: Cédric Le Goater --- hw/intc/pnv_xive2_regs.h | 5 +++++ hw/intc/pnv_xive2.c | 4 ++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/hw/intc/pnv_xive2_regs.h b/hw/intc/pnv_xive2_regs.h index 084fccc8d3e9..46d4fb378135 100644 --- a/hw/intc/pnv_xive2_regs.h +++ b/hw/intc/pnv_xive2_regs.h @@ -31,6 +31,11 @@ #define CQ_XIVE_CAP_VP_INT_PRIO_8 3 #define CQ_XIVE_CAP_BLOCK_ID_WIDTH PPC_BITMASK(12, 13) +#define CQ_XIVE_CAP_PHB_PQ_DISABLE PPC_BIT(56) +#define CQ_XIVE_CAP_PHB_ABT PPC_BIT(57) +#define CQ_XIVE_CAP_EXPLOITATION_MODE PPC_BIT(58) +#define CQ_XIVE_CAP_STORE_EOI PPC_BIT(59) + /* XIVE2 Configuration */ #define X_CQ_XIVE_CFG 0x03 #define CQ_XIVE_CFG 0x018 diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index 186ab66e105d..cb12cea14fc6 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/pnv_xive2.c @@ -1708,9 +1708,9 @@ static const MemoryRegionOps pnv_xive2_nvpg_ops = { }; /* - * POWER10 default capabilities: 0x2000120076f00000 + * POWER10 default capabilities: 0x2000120076f000FC */ -#define PNV_XIVE2_CAPABILITIES 0x2000120076f00000 +#define PNV_XIVE2_CAPABILITIES 0x2000120076f000FC /* * POWER10 default configuration: 0x0030000033000000