@@ -647,21 +647,18 @@ static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
return gen_arith(ctx, a, EXT_NONE, gen_add_uw);
}
+static void gen_slli_uw(TCGv dest, TCGv src, target_long shamt)
+{
+ if (shamt < 32) {
+ tcg_gen_deposit_z_tl(dest, src, shamt, 32);
+ } else {
+ tcg_gen_shli_tl(dest, src, shamt);
+ }
+}
+
static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
-
- TCGv source1 = tcg_temp_new();
- gen_get_gpr(ctx, source1, a->rs1);
-
- if (a->shamt < 32) {
- tcg_gen_deposit_z_tl(source1, source1, a->shamt, 32);
- } else {
- tcg_gen_shli_tl(source1, source1, a->shamt);
- }
-
- gen_set_gpr(ctx, a->rd, source1);
- tcg_temp_free(source1);
- return true;
+ return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);
}
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/riscv/insn_trans/trans_rvb.c.inc | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-)