@@ -62,6 +62,9 @@
#define RTC_ADDR 0xffa60000
#define RTC_IRQ 26
+#define BBRAM_ADDR 0xffcd0000
+#define BBRAM_IRQ 11
+
#define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */
static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
@@ -222,6 +225,22 @@ static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s,
qdev_realize(DEVICE(&s->rpu_cluster), NULL, &error_fatal);
}
+static void xlnx_zynqmp_create_bbram(XlnxZynqMPState *s, qemu_irq *gic)
+{
+ SysBusDevice *sbd;
+
+ object_initialize_child_with_props(OBJECT(s), "bbram", &s->bbram,
+ sizeof(s->bbram), TYPE_XLNX_BBRAM,
+ &error_fatal,
+ "crc-zpads", "1",
+ NULL);
+ sbd = SYS_BUS_DEVICE(&s->bbram);
+
+ sysbus_realize(sbd, &error_fatal);
+ sysbus_mmio_map(sbd, 0, BBRAM_ADDR);
+ sysbus_connect_irq(sbd, 0, gic[BBRAM_IRQ]);
+}
+
static void xlnx_zynqmp_init(Object *obj)
{
MachineState *ms = MACHINE(qdev_get_machine());
@@ -616,6 +635,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, RTC_ADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, gic_spi[RTC_IRQ]);
+ xlnx_zynqmp_create_bbram(s, gic_spi);
+
for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
if (!object_property_set_uint(OBJECT(&s->gdma[i]), "bus-width", 128,
errp)) {
@@ -36,6 +36,7 @@
#include "qom/object.h"
#include "net/can_emu.h"
#include "hw/dma/xlnx_csu_dma.h"
+#include "hw/nvram/xlnx-bbram.h"
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
@@ -95,6 +96,7 @@ struct XlnxZynqMPState {
MemoryRegion *ddr_ram;
MemoryRegion ddr_ram_low, ddr_ram_high;
+ XlnxBBRam bbram;
CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
Connect the support for Xilinx ZynqMP Battery-Backed RAM (BBRAM) Signed-off-by: Tong Ho <tong.ho@xilinx.com> --- hw/arm/xlnx-zynqmp.c | 21 +++++++++++++++++++++ include/hw/arm/xlnx-zynqmp.h | 2 ++ 2 files changed, 23 insertions(+)