diff mbox series

[PULL,03/33] target/riscv: Correct a comment in riscv_csrrw()

Message ID 20210901020958.458454-4-alistair.francis@opensource.wdc.com (mailing list archive)
State New, archived
Headers show
Series [PULL,01/33] hw/char: Add config for shakti uart | expand

Commit Message

Alistair Francis Sept. 1, 2021, 2:09 a.m. UTC
From: Bin Meng <bmeng.cn@gmail.com>

When privilege check fails, RISCV_EXCP_ILLEGAL_INST is returned,
not -1 (RISCV_EXCP_NONE).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210807141025.31808-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9a4ed18ac5..e747fbe0e9 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1423,7 +1423,7 @@  RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
     target_ulong old_value;
     RISCVCPU *cpu = env_archcpu(env);
 
-    /* check privileges and return -1 if check fails */
+    /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
 #if !defined(CONFIG_USER_ONLY)
     int effective_priv = env->priv;
     int read_only = get_field(csrno, 0xC00) == 3;