| Message ID | 20210901032724.23256-4-bmeng.cn@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | hw/arm: xilinx_zynq: Fix upstream U-Boot boot failure | expand |
On Wed, Sep 1, 2021 at 1:28 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > Currently the clock/reset check is done in uart_receive(), but we > can move the check to uart_can_receive() which is earlier. > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > > --- > > Changes in v2: > - avoid declaring variables mid-scope > > hw/char/cadence_uart.c | 17 ++++++++++------- > 1 file changed, 10 insertions(+), 7 deletions(-) > > diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c > index 154be34992..fff8be3619 100644 > --- a/hw/char/cadence_uart.c > +++ b/hw/char/cadence_uart.c > @@ -235,8 +235,16 @@ static void uart_parameters_setup(CadenceUARTState *s) > static int uart_can_receive(void *opaque) > { > CadenceUARTState *s = opaque; > - int ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE); > - uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE; > + int ret; > + uint32_t ch_mode; > + > + /* ignore characters when unclocked or in reset */ > + if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) { > + return 0; > + } > + > + ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE); > + ch_mode = s->r[R_MR] & UART_MR_CHMODE; > > if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) { > ret = MIN(ret, CADENCE_UART_RX_FIFO_SIZE - s->rx_count); > @@ -358,11 +366,6 @@ static void uart_receive(void *opaque, const uint8_t *buf, int size) > CadenceUARTState *s = opaque; > uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE; > > - /* ignore characters when unclocked or in reset */ > - if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) { > - return; > - } > - > if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) { > uart_write_rx_fifo(opaque, buf, size); > } > -- > 2.25.1 > >
On 9/1/21 5:27 AM, Bin Meng wrote: > Currently the clock/reset check is done in uart_receive(), but we > can move the check to uart_can_receive() which is earlier. > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com> > > --- > > Changes in v2: > - avoid declaring variables mid-scope > > hw/char/cadence_uart.c | 17 ++++++++++------- > 1 file changed, 10 insertions(+), 7 deletions(-) Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index 154be34992..fff8be3619 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -235,8 +235,16 @@ static void uart_parameters_setup(CadenceUARTState *s) static int uart_can_receive(void *opaque) { CadenceUARTState *s = opaque; - int ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE); - uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE; + int ret; + uint32_t ch_mode; + + /* ignore characters when unclocked or in reset */ + if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) { + return 0; + } + + ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE); + ch_mode = s->r[R_MR] & UART_MR_CHMODE; if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) { ret = MIN(ret, CADENCE_UART_RX_FIFO_SIZE - s->rx_count); @@ -358,11 +366,6 @@ static void uart_receive(void *opaque, const uint8_t *buf, int size) CadenceUARTState *s = opaque; uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE; - /* ignore characters when unclocked or in reset */ - if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) { - return; - } - if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) { uart_write_rx_fifo(opaque, buf, size); }
Currently the clock/reset check is done in uart_receive(), but we can move the check to uart_can_receive() which is earlier. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> --- Changes in v2: - avoid declaring variables mid-scope hw/char/cadence_uart.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-)