| Message ID | 20210902112520.475901-18-anup.patel@wdc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | QEMU RISC-V AIA support | expand |
On Thu, Sep 2, 2021 at 10:03 PM Anup Patel <anup.patel@wdc.com> wrote: > > We add "x-aia" command-line option for RISC-V HART using which > allows users to force enable CPU AIA CSRs without changing the > interrupt controller available in RISC-V machine. > > Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 5 +++++ > target/riscv/cpu.h | 1 + > 2 files changed, 6 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index e0f4ae4224..9723d54eaf 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -452,6 +452,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > } > } > > + if (cpu->cfg.aia) { > + riscv_set_feature(env, RISCV_FEATURE_AIA); > + } > + > set_resetvec(env, cpu->cfg.resetvec); > > /* If only XLEN is set for misa, then set misa from properties */ > @@ -672,6 +676,7 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), > DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), > DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), > + DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false), > > DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), > DEFINE_PROP_END_OF_LIST(), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 16a4596433..cab9e90153 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -337,6 +337,7 @@ struct RISCVCPU { > bool mmu; > bool pmp; > bool epmp; > + bool aia; > uint64_t resetvec; > } cfg; > }; > -- > 2.25.1 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e0f4ae4224..9723d54eaf 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -452,6 +452,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } } + if (cpu->cfg.aia) { + riscv_set_feature(env, RISCV_FEATURE_AIA); + } + set_resetvec(env, cpu->cfg.resetvec); /* If only XLEN is set for misa, then set misa from properties */ @@ -672,6 +676,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), + DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false), DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), DEFINE_PROP_END_OF_LIST(), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 16a4596433..cab9e90153 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -337,6 +337,7 @@ struct RISCVCPU { bool mmu; bool pmp; bool epmp; + bool aia; uint64_t resetvec; } cfg; };
We add "x-aia" command-line option for RISC-V HART using which allows users to force enable CPU AIA CSRs without changing the interrupt controller available in RISC-V machine. Signed-off-by: Anup Patel <anup.patel@wdc.com> --- target/riscv/cpu.c | 5 +++++ target/riscv/cpu.h | 1 + 2 files changed, 6 insertions(+)