| Message ID | 20210903203116.80628-5-danielhb413@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | PMU-EBB support for PPC64 TCG | expand |
On Fri, Sep 03, 2021 at 05:31:05PM -0300, Daniel Henrique Barboza wrote: 65;6402;1c> This patch enable all PMCs but PMC5 to count cycles. To do that we > need to implement MMCR1 bits where the event are stored, retrieve > them, see if the PMC was configured with a PM_CYC event, and > calculate cycles if that's the case. > > PowerISA v3.1 defines the following conditions to count cycles: > > - PMC1 set with the event 0xF0; > - PMC6, which always count cycles > > However, the PowerISA also defines a range of 'implementation dependent' > events that the chip can use in the 0x01-0xBF range. Turns out that IBM > POWER chips implements some non-ISA events, and the Linux kernel makes uses > of them. For instance, 0x1E is an implementation specific event that > counts cycles in PMCs 1-4 that the kernel uses. Let's also support 0x1E > to count cycles to allow for existing kernels to behave properly with the > PMU. > > Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> > --- > target/ppc/cpu.h | 11 +++++++++ > target/ppc/power8_pmu.c | 52 +++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 63 insertions(+) > > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > index a9b31736af..74698a3600 100644 > --- a/target/ppc/cpu.h > +++ b/target/ppc/cpu.h > @@ -352,6 +352,17 @@ typedef struct ppc_v3_pate_t { > /* MMCR0 userspace r/w mask */ > #define MMCR0_UREG_MASK (MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE) > > +#define MMCR1_EVT_SIZE 8 > +/* extract64() does a right shift before extracting */ > +#define MMCR1_PMC1SEL_START 32 > +#define MMCR1_PMC1EVT_EXTR (64 - MMCR1_PMC1SEL_START - MMCR1_EVT_SIZE) > +#define MMCR1_PMC2SEL_START 40 > +#define MMCR1_PMC2EVT_EXTR (64 - MMCR1_PMC2SEL_START - MMCR1_EVT_SIZE) > +#define MMCR1_PMC3SEL_START 48 > +#define MMCR1_PMC3EVT_EXTR (64 - MMCR1_PMC3SEL_START - MMCR1_EVT_SIZE) > +#define MMCR1_PMC4SEL_START 56 > +#define MMCR1_PMC4EVT_EXTR (64 - MMCR1_PMC4SEL_START - MMCR1_EVT_SIZE) > + > /* LPCR bits */ > #define LPCR_VPM0 PPC_BIT(0) > #define LPCR_VPM1 PPC_BIT(1) > diff --git a/target/ppc/power8_pmu.c b/target/ppc/power8_pmu.c > index 47de38a99e..3f7b305f4f 100644 > --- a/target/ppc/power8_pmu.c > +++ b/target/ppc/power8_pmu.c > @@ -31,10 +31,62 @@ static void update_PMC_PM_CYC(CPUPPCState *env, int sprn, > env->spr[sprn] += time_delta; > } > > +static void update_programmable_PMC_reg(CPUPPCState *env, int sprn, > + uint64_t time_delta) > +{ > + uint8_t event, evt_extr; > + > + switch (sprn) { > + case SPR_POWER_PMC1: > + evt_extr = MMCR1_PMC1EVT_EXTR; > + break; > + case SPR_POWER_PMC2: > + evt_extr = MMCR1_PMC2EVT_EXTR; > + break; > + case SPR_POWER_PMC3: > + evt_extr = MMCR1_PMC3EVT_EXTR; > + break; > + case SPR_POWER_PMC4: > + evt_extr = MMCR1_PMC4EVT_EXTR; > + break; > + default: > + return; > + } > + > + event = extract64(env->spr[SPR_POWER_MMCR1], evt_extr, MMCR1_EVT_SIZE); > + > + /* > + * MMCR0_PMC1SEL = 0xF0 is the architected PowerISA v3.1 event > + * that counts cycles using PMC1. > + * > + * IBM POWER chips also has support for an implementation dependent > + * event, 0x1E, that enables cycle counting on PMCs 1-4. The > + * Linux kernel makes extensive use of 0x1E, so let's also support > + * it. > + */ > + switch (event) { > + case 0xF0: > + if (sprn == SPR_POWER_PMC1) { > + update_PMC_PM_CYC(env, sprn, time_delta); > + } > + break; > + case 0x1E: > + update_PMC_PM_CYC(env, sprn, time_delta); > + break; > + default: > + return; > + } > +} > + > static void update_cycles_PMCs(CPUPPCState *env) > { > uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); > uint64_t time_delta = now - env->pmu_base_time; > + int sprn; > + > + for (sprn = SPR_POWER_PMC1; sprn < SPR_POWER_PMC5; sprn++) { > + update_programmable_PMC_reg(env, sprn, time_delta); > + } > > update_PMC_PM_CYC(env, SPR_POWER_PMC6, time_delta); > }
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index a9b31736af..74698a3600 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -352,6 +352,17 @@ typedef struct ppc_v3_pate_t { /* MMCR0 userspace r/w mask */ #define MMCR0_UREG_MASK (MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE) +#define MMCR1_EVT_SIZE 8 +/* extract64() does a right shift before extracting */ +#define MMCR1_PMC1SEL_START 32 +#define MMCR1_PMC1EVT_EXTR (64 - MMCR1_PMC1SEL_START - MMCR1_EVT_SIZE) +#define MMCR1_PMC2SEL_START 40 +#define MMCR1_PMC2EVT_EXTR (64 - MMCR1_PMC2SEL_START - MMCR1_EVT_SIZE) +#define MMCR1_PMC3SEL_START 48 +#define MMCR1_PMC3EVT_EXTR (64 - MMCR1_PMC3SEL_START - MMCR1_EVT_SIZE) +#define MMCR1_PMC4SEL_START 56 +#define MMCR1_PMC4EVT_EXTR (64 - MMCR1_PMC4SEL_START - MMCR1_EVT_SIZE) + /* LPCR bits */ #define LPCR_VPM0 PPC_BIT(0) #define LPCR_VPM1 PPC_BIT(1) diff --git a/target/ppc/power8_pmu.c b/target/ppc/power8_pmu.c index 47de38a99e..3f7b305f4f 100644 --- a/target/ppc/power8_pmu.c +++ b/target/ppc/power8_pmu.c @@ -31,10 +31,62 @@ static void update_PMC_PM_CYC(CPUPPCState *env, int sprn, env->spr[sprn] += time_delta; } +static void update_programmable_PMC_reg(CPUPPCState *env, int sprn, + uint64_t time_delta) +{ + uint8_t event, evt_extr; + + switch (sprn) { + case SPR_POWER_PMC1: + evt_extr = MMCR1_PMC1EVT_EXTR; + break; + case SPR_POWER_PMC2: + evt_extr = MMCR1_PMC2EVT_EXTR; + break; + case SPR_POWER_PMC3: + evt_extr = MMCR1_PMC3EVT_EXTR; + break; + case SPR_POWER_PMC4: + evt_extr = MMCR1_PMC4EVT_EXTR; + break; + default: + return; + } + + event = extract64(env->spr[SPR_POWER_MMCR1], evt_extr, MMCR1_EVT_SIZE); + + /* + * MMCR0_PMC1SEL = 0xF0 is the architected PowerISA v3.1 event + * that counts cycles using PMC1. + * + * IBM POWER chips also has support for an implementation dependent + * event, 0x1E, that enables cycle counting on PMCs 1-4. The + * Linux kernel makes extensive use of 0x1E, so let's also support + * it. + */ + switch (event) { + case 0xF0: + if (sprn == SPR_POWER_PMC1) { + update_PMC_PM_CYC(env, sprn, time_delta); + } + break; + case 0x1E: + update_PMC_PM_CYC(env, sprn, time_delta); + break; + default: + return; + } +} + static void update_cycles_PMCs(CPUPPCState *env) { uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); uint64_t time_delta = now - env->pmu_base_time; + int sprn; + + for (sprn = SPR_POWER_PMC1; sprn < SPR_POWER_PMC5; sprn++) { + update_programmable_PMC_reg(env, sprn, time_delta); + } update_PMC_PM_CYC(env, SPR_POWER_PMC6, time_delta); }
This patch enable all PMCs but PMC5 to count cycles. To do that we need to implement MMCR1 bits where the event are stored, retrieve them, see if the PMC was configured with a PM_CYC event, and calculate cycles if that's the case. PowerISA v3.1 defines the following conditions to count cycles: - PMC1 set with the event 0xF0; - PMC6, which always count cycles However, the PowerISA also defines a range of 'implementation dependent' events that the chip can use in the 0x01-0xBF range. Turns out that IBM POWER chips implements some non-ISA events, and the Linux kernel makes uses of them. For instance, 0x1E is an implementation specific event that counts cycles in PMCs 1-4 that the kernel uses. Let's also support 0x1E to count cycles to allow for existing kernels to behave properly with the PMU. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> --- target/ppc/cpu.h | 11 +++++++++ target/ppc/power8_pmu.c | 52 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+)