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Sat, 11 Sep 2021 07:00:21 -0700 (PDT) Received: from localhost.localdomain ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id u15sm213052lfk.26.2021.09.11.07.00.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Sep 2021 07:00:20 -0700 (PDT) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v11 01/16] target/riscv: Introduce temporary in gen_add_uw() Date: Sat, 11 Sep 2021 16:00:01 +0200 Message-Id: <20210911140016.834071-2-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210911140016.834071-1-philipp.tomsich@vrull.eu> References: <20210911140016.834071-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::230; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lj1-x230.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Bin Meng , Alistair Francis , Philipp Tomsich Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Following the recent changes in translate.c, gen_add_uw() causes failures on CF3 and SPEC2017 due to the reuse of arg1. Fix these regressions by introducing a temporary. Signed-off-by: Philipp Tomsich Fixes: 191d1dafae9c ("target/riscv: Add DisasExtend to gen_arith*") Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Richard Henderson --- (no changes since v10) Changes in v10: - new patch target/riscv/insn_trans/trans_rvb.c.inc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index b72e76255c..c0a6e25826 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -624,8 +624,10 @@ GEN_TRANS_SHADD_UW(3) static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2) { - tcg_gen_ext32u_tl(arg1, arg1); - tcg_gen_add_tl(ret, arg1, arg2); + TCGv t = tcg_temp_new(); + tcg_gen_ext32u_tl(t, arg1); + tcg_gen_add_tl(ret, t, arg2); + tcg_temp_free(t); } static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)