diff mbox series

[RFC,04/10] target/riscv: rvb: add generalized shuffle instructions

Message ID 20210918062816.7546-5-tangxingxin1008@gmail.com (mailing list archive)
State New, archived
Headers show
Series add the rest of riscv bitmapip-0.93 instructions | expand

Commit Message

eric tang Sept. 18, 2021, 6:28 a.m. UTC 
Signed-off-by: Eric Tang <tangxingxin1008@gmail.com>
diff mbox series

Patch

diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index e31cf582ca..19c64756c5 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -123,3 +123,85 @@  target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2)
 {
     return do_clmulr(rs1, rs2, TARGET_LONG_BITS);
 }
+
+static target_ulong shuffle_stage(target_ulong src,
+                                  uint64_t maskl,
+                                  uint64_t maskr,
+                                  int n)
+{
+    target_ulong x = src & ~(maskl | maskr);
+    x |= ((src << n) & maskl) | ((src >> n) & maskr);
+    return x;
+}
+
+static target_ulong do_shfl(target_ulong rs1,
+                            target_ulong rs2,
+                            int bits)
+{
+    target_ulong x = rs1;
+    int shamt = rs2 & ((bits - 1) >> 1);
+
+    if (shamt & 16) {
+        x = shuffle_stage(x, 0x0000ffff00000000LL, 0x00000000ffff0000LL, 16);
+    }
+    if (shamt & 8) {
+        x = shuffle_stage(x, 0x00ff000000ff0000LL, 0x0000ff000000ff00LL, 8);
+    }
+    if (shamt & 4) {
+        x = shuffle_stage(x, 0x0f000f000f000f00LL, 0x00f000f000f000f0LL, 4);
+    }
+    if (shamt & 2) {
+        x = shuffle_stage(x, 0x3030303030303030LL, 0x0c0c0c0c0c0c0c0cLL, 2);
+    }
+    if (shamt & 1) {
+        x = shuffle_stage(x, 0x4444444444444444LL, 0x2222222222222222LL, 1);
+    }
+
+    return x;
+}
+
+static target_ulong do_unshfl(target_ulong rs1,
+                              target_ulong rs2,
+                              int bits)
+{
+    target_ulong x = rs1;
+    int shamt = rs2 & ((bits - 1) >> 1);
+
+    if (shamt & 1) {
+        x = shuffle_stage(x, 0x4444444444444444LL, 0x2222222222222222LL, 1);
+    }
+    if (shamt & 2) {
+        x = shuffle_stage(x, 0x3030303030303030LL, 0x0c0c0c0c0c0c0c0cLL, 2);
+    }
+    if (shamt & 4) {
+        x = shuffle_stage(x, 0x0f000f000f000f00LL, 0x00f000f000f000f0LL, 4);
+    }
+    if (shamt & 8) {
+        x = shuffle_stage(x, 0x00ff000000ff0000LL, 0x0000ff000000ff00LL, 8);
+    }
+    if (shamt & 16) {
+        x = shuffle_stage(x, 0x0000ffff00000000LL, 0x00000000ffff0000LL, 16);
+    }
+
+    return x;
+}
+
+target_ulong HELPER(shfl)(target_ulong rs1, target_ulong rs2)
+{
+    return do_shfl(rs1, rs2, TARGET_LONG_BITS);
+}
+
+target_ulong HELPER(unshfl)(target_ulong rs1, target_ulong rs2)
+{
+    return do_unshfl(rs1, rs2, TARGET_LONG_BITS);
+}
+
+target_ulong HELPER(shflw)(target_ulong rs1, target_ulong rs2)
+{
+    return do_shfl(rs1, rs2, 32);
+}
+
+target_ulong HELPER(unshflw)(target_ulong rs1, target_ulong rs2)
+{
+    return do_unshfl(rs1, rs2, 32);
+}
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 7cbcee48e6..015526faf0 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -66,6 +66,10 @@  DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(clmulh, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(shfl, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(unshfl, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(shflw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(unshflw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 
 /* Special functions */
 DEF_HELPER_2(csrr, tl, env, int)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 989ea3c602..e70a38a5c6 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -23,6 +23,7 @@ 
 %rd        7:5
 %sh5       20:5
 
+%sh6    20:6
 %sh7    20:7
 %csr    20:12
 %rm     12:3
@@ -63,6 +64,7 @@ 
 @j       ....................      ..... ....... &j      imm=%imm_j          %rd
 
 @sh      ......  ...... .....  ... ..... ....... &shift  shamt=%sh7     %rs1 %rd
+@sh6     ......  ...... .....  ... ..... ....... &shift  shamt=%sh6     %rs1 %rd
 @csr     ............   .....  ... ..... .......               %csr     %rs1 %rd
 
 @atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0     %rs1 %rd
@@ -695,6 +697,8 @@  sh3add     0010000 .......... 110 ..... 0110011 @r
 clmul      0000101 .......... 001 ..... 0110011 @r
 clmulh     0000101 .......... 011 ..... 0110011 @r
 clmulr     0000101 .......... 010 ..... 0110011 @r
+shfl       0000100 .......... 001 ..... 0110011 @r
+unshfl     0000100 .......... 101 ..... 0110011 @r
 cmix       .....11 .......... 001 ..... 0110011 @r4
 cmov       .....11 .......... 101 ..... 0110011 @r4
 
@@ -707,6 +711,8 @@  sroi       00100. ........... 101 ..... 0010011 @sh
 rori       01100. ........... 101 ..... 0010011 @sh
 grevi      01101. ........... 101 ..... 0010011 @sh
 gorci      00101. ........... 101 ..... 0010011 @sh
+shfli      000010 ........... 001 ..... 0010011 @sh6
+unshfli    000010 ........... 101 ..... 0010011 @sh6
 
 # *** RV64B Standard Extension (in addition to RV32B) ***
 clzw       0110000 00000 ..... 001 ..... 0011011 @r2
@@ -729,6 +735,8 @@  sh1add_uw  0010000 .......... 010 ..... 0111011 @r
 sh2add_uw  0010000 .......... 100 ..... 0111011 @r
 sh3add_uw  0010000 .......... 110 ..... 0111011 @r
 add_uw     0000100 .......... 000 ..... 0111011 @r
+shflw      0000100 .......... 001 ..... 0111011 @r
+unshflw    0000100 .......... 101 ..... 0111011 @r
 
 bsetiw     0010100 .......... 001 ..... 0011011 @sh5
 bclriw     0100100 .......... 001 ..... 0011011 @sh5
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index ebcbb341cb..cbd48b4c8c 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -321,6 +321,36 @@  static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
     return gen_shift_imm_tl(ctx, a, EXT_ZERO, gen_helper_gorc);
 }
 
+static bool trans_shfl(DisasContext *ctx, arg_shfl *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, EXT_NONE, gen_helper_shfl);
+}
+
+static bool trans_unshfl(DisasContext *ctx, arg_unshfl *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    return gen_arith(ctx, a, EXT_NONE, gen_helper_unshfl);
+}
+
+static bool trans_shfli(DisasContext *ctx, arg_shfli *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    if (a->shamt >= (TARGET_LONG_BITS / 2)) {
+        return false;
+    }
+    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_helper_shfl);
+}
+
+static bool trans_unshfli(DisasContext *ctx, arg_unshfli *a)
+{
+    REQUIRE_EXT(ctx, RVB);
+    if (a->shamt >= (TARGET_LONG_BITS / 2)) {
+        return false;
+    }
+    return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_helper_unshfl);
+}
+
 #define GEN_TRANS_CLMUL(NAME)                               \
 static bool trans_##NAME(DisasContext *ctx, arg_##NAME * a) \
 {                                                           \
@@ -703,3 +733,19 @@  static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
     REQUIRE_EXT(ctx, RVB);
     return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);
 }
+
+static bool trans_shflw(DisasContext *ctx, arg_shflw *a)
+{
+    REQUIRE_64BIT(ctx);
+    REQUIRE_EXT(ctx, RVB);
+    ctx->w = true;
+    return gen_arith(ctx, a, EXT_ZERO, gen_helper_shflw);
+}
+
+static bool trans_unshflw(DisasContext *ctx, arg_unshflw *a)
+{
+    REQUIRE_64BIT(ctx);
+    REQUIRE_EXT(ctx, RVB);
+    ctx->w = true;
+    return gen_arith(ctx, a, EXT_ZERO, gen_helper_unshflw);
+}