[PULL,04/26] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties

Commit Message

Alistair Francis Oct. 7, 2021, 6:47 a.m. UTC

From: Philipp Tomsich <[e-mail]>

The bitmanipulation ISA extensions will be ratified as individual
small extension packages instead of a large B-extension.  The first
new instructions through the door (these have completed public review)
are Zb[abcs].

This adds new 'x-zba', 'x-zbb', 'x-zbc' and 'x-zbs' properties for
these in target/riscv/cpu.[ch].

Signed-off-by: Philipp Tomsich <[e-mail]>
Reviewed-by: Richard Henderson <[e-mail]>
Reviewed-by: Alistair Francis <[e-mail]>
Reviewed-by: Bin Meng <[e-mail]>
Message-id: [e-mail]
Signed-off-by: Alistair Francis <[e-mail]>
---
 target/riscv/cpu.h | 4 ++++
 target/riscv/cpu.c | 4 ++++
 2 files changed, 8 insertions(+)

Patch

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5896aca346..1a38723f2c 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -293,6 +293,10 @@  struct RISCVCPU {
         bool ext_u;
         bool ext_h;
         bool ext_v;
+        bool ext_zba;
+        bool ext_zbb;
+        bool ext_zbc;
+        bool ext_zbs;
         bool ext_counters;
         bool ext_ifencei;
         bool ext_icsr;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7c626d89cd..785a3a8d19 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -617,6 +617,10 @@  static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
     /* This is experimental so mark with 'x-' */
     DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false),
+    DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false),
+    DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
+    DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
+    DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
     DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
     DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
     DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),