| Message ID | 20211015074627.3957162-40-frank.chang@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | support vector extension v1.0 | expand |
On Fri, Oct 15, 2021 at 6:25 PM <frank.chang@sifive.com> wrote: > > From: Frank Chang <frank.chang@sifive.com> > > Signed-off-by: Frank Chang <frank.chang@sifive.com> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/insn32.decode | 2 +- > target/riscv/insn_trans/trans_rvv.c.inc | 10 ++++++++-- > 2 files changed, 9 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index d139c0aade7..3ac5162aeb7 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -632,7 +632,7 @@ vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm > vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm > vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm > vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm > -viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm > +viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm > vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm > vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r > vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2 > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc > index 538a32a605a..3751496676f 100644 > --- a/target/riscv/insn_trans/trans_rvv.c.inc > +++ b/target/riscv/insn_trans/trans_rvv.c.inc > @@ -2756,12 +2756,18 @@ GEN_M_TRANS(vmsbf_m) > GEN_M_TRANS(vmsif_m) > GEN_M_TRANS(vmsof_m) > > -/* Vector Iota Instruction */ > +/* > + * Vector Iota Instruction > + * > + * 1. The destination register cannot overlap the source register. > + * 2. If masked, cannot overlap the mask register ('v0'). > + * 3. An illegal instruction exception is raised if vstart is non-zero. > + */ > static bool trans_viota_m(DisasContext *s, arg_viota_m *a) > { > if (require_rvv(s) && > vext_check_isa_ill(s) && > - require_noover(a->rd, s->lmul, a->rs2, 0) && > + !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs2, 1) && > require_vm(a->vm, a->rd) && > require_align(a->rd, s->lmul)) { > uint32_t data = 0; > -- > 2.25.1 > >
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index d139c0aade7..3ac5162aeb7 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -632,7 +632,7 @@ vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm -viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm +viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2 diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 538a32a605a..3751496676f 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2756,12 +2756,18 @@ GEN_M_TRANS(vmsbf_m) GEN_M_TRANS(vmsif_m) GEN_M_TRANS(vmsof_m) -/* Vector Iota Instruction */ +/* + * Vector Iota Instruction + * + * 1. The destination register cannot overlap the source register. + * 2. If masked, cannot overlap the mask register ('v0'). + * 3. An illegal instruction exception is raised if vstart is non-zero. + */ static bool trans_viota_m(DisasContext *s, arg_viota_m *a) { if (require_rvv(s) && vext_check_isa_ill(s) && - require_noover(a->rd, s->lmul, a->rs2, 0) && + !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs2, 1) && require_vm(a->vm, a->rd) && require_align(a->rd, s->lmul)) { uint32_t data = 0;