| Message ID | 20211019152438.269077-15-richard.henderson@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/riscv: Rationalize XLEN and operand length | expand |
On Wed, Oct 20, 2021 at 2:18 AM Richard Henderson <richard.henderson@linaro.org> wrote: > > Allocate 8 columns per register name. > > Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> This probably isn't required though as there is already a similar patch in my tree: https://github.com/alistair23/qemu/tree/riscv-to-apply.next Alistair > --- > target/riscv/cpu.c | 7 ++++--- > 1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 4e1920d5f0..f352c2b74c 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -240,7 +240,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) > qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); > } > #endif > - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); > + qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", "pc", env->pc); > #ifndef CONFIG_USER_ONLY > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); > qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus); > @@ -290,15 +290,16 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) > #endif > > for (i = 0; i < 32; i++) { > - qemu_fprintf(f, " %s " TARGET_FMT_lx, > + qemu_fprintf(f, " %-8s " TARGET_FMT_lx, > riscv_int_regnames[i], env->gpr[i]); > if ((i & 3) == 3) { > qemu_fprintf(f, "\n"); > } > } > + > if (flags & CPU_DUMP_FPU) { > for (i = 0; i < 32; i++) { > - qemu_fprintf(f, " %s %016" PRIx64, > + qemu_fprintf(f, " %-8s %016" PRIx64, > riscv_fpr_regnames[i], env->fpr[i]); > if ((i & 3) == 3) { > qemu_fprintf(f, "\n"); > -- > 2.25.1 > >
On 10/19/21 3:10 PM, Alistair Francis wrote: > On Wed, Oct 20, 2021 at 2:18 AM Richard Henderson > <richard.henderson@linaro.org> wrote: >> >> Allocate 8 columns per register name. >> >> Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> >> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > > This probably isn't required though as there is already a similar > patch in my tree: > https://github.com/alistair23/qemu/tree/riscv-to-apply.next Ah yes. Just drop my version, I think. I can rebase on your branch too, since I see a conflict with that patch. r~
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4e1920d5f0..f352c2b74c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -240,7 +240,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); } #endif - qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); + qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", "pc", env->pc); #ifndef CONFIG_USER_ONLY qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus); @@ -290,15 +290,16 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) #endif for (i = 0; i < 32; i++) { - qemu_fprintf(f, " %s " TARGET_FMT_lx, + qemu_fprintf(f, " %-8s " TARGET_FMT_lx, riscv_int_regnames[i], env->gpr[i]); if ((i & 3) == 3) { qemu_fprintf(f, "\n"); } } + if (flags & CPU_DUMP_FPU) { for (i = 0; i < 32; i++) { - qemu_fprintf(f, " %s %016" PRIx64, + qemu_fprintf(f, " %-8s %016" PRIx64, riscv_fpr_regnames[i], env->fpr[i]); if ((i & 3) == 3) { qemu_fprintf(f, "\n");