diff mbox series

[25/33] target/ppc: added the instructions PLXV and PSTXV

Message ID 20211021194547.672988-26-matheus.ferst@eldorado.org.br (mailing list archive)
State New, archived
Headers show
Series PowerISA v3.1 instruction batch | expand

Commit Message

Matheus K. Ferst Oct. 21, 2021, 7:45 p.m. UTC 
From: "Lucas Mateus Castro (alqotel)" <lucas.castro@eldorado.org.br>

Implemented the instructions plxv and pstxv using decodetree

Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.castro@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
 target/ppc/insn64.decode            | 10 ++++++++++
 target/ppc/translate/vsx-impl.c.inc | 16 ++++++++++++++++
 2 files changed, 26 insertions(+)

Comments

Richard Henderson Oct. 23, 2021, 8:56 p.m. UTC | #1 
On 10/21/21 12:45 PM, matheus.ferst@eldorado.org.br wrote:
> From: "Lucas Mateus Castro (alqotel)"<lucas.castro@eldorado.org.br>
> 
> Implemented the instructions plxv and pstxv using decodetree
> 
> Signed-off-by: Lucas Mateus Castro (alqotel)<lucas.castro@eldorado.org.br>
> Signed-off-by: Matheus Ferst<matheus.ferst@eldorado.org.br>
> ---
>   target/ppc/insn64.decode            | 10 ++++++++++
>   target/ppc/translate/vsx-impl.c.inc | 16 ++++++++++++++++
>   2 files changed, 26 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~
diff mbox series

Patch

diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 48756cd4ca..093439b370 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -23,6 +23,9 @@ 
 @PLS_D          ...... .. ... r:1 .. .................. \
                 ...... rt:5 ra:5 ................       \
                 &PLS_D si=%pls_si
+@8LS_D_TSX      ...... .. . .. r:1 .. .................. \
+                ..... rt:6 ra:5 ................         \
+                &PLS_D si=%pls_si
 
 ### Fixed-Point Load Instructions
 
@@ -137,3 +140,10 @@  PSTFD           000001 10 0--.-- .................. \
   PNOP          ................................        \
                 --------------------------------        @PNOP
 }
+
+### VSX instructions
+
+PLXV            000001 00 0--.-- .................. \
+                11001 ...... ..... ................     @8LS_D_TSX
+PSTXV           000001 00 0--.-- .................. \
+                11011 ...... ..... ................     @8LS_D_TSX
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index d3e2e4ff8e..64c452ee24 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -2044,6 +2044,20 @@  static bool do_lstxv_D(DisasContext *ctx, arg_D *a, bool store, bool paired)
     return do_lstxv(ctx, a->ra, tcg_constant_tl(a->si), a->rt, store, paired);
 }
 
+static bool do_lstxv_PLS_D(DisasContext *ctx, arg_PLS_D *a,
+                           bool store, bool paired)
+{
+    arg_D d;
+    REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+    REQUIRE_VSX(ctx);
+
+    if (!resolve_PLS_D(ctx, &d, a)) {
+        return true;
+    }
+
+    return do_lstxv(ctx, d.ra, tcg_constant_tl(d.si), d.rt, store, paired);
+}
+
 static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool store, bool paired)
 {
     if (paired) {
@@ -2069,6 +2083,8 @@  TRANS(STXVX, do_lstxv_X, true, false)
 TRANS(LXVX, do_lstxv_X, false, false)
 TRANS(STXVPX, do_lstxv_X, true, true)
 TRANS(LXVPX, do_lstxv_X, false, true)
+TRANS64(PSTXV, do_lstxv_PLS_D, true, false)
+TRANS64(PLXV, do_lstxv_PLS_D, false, false)
 
 #undef GEN_XX2FORM
 #undef GEN_XX3FORM