diff mbox series

[07/33] target/ppc: Implement cntlzdm

Message ID 20211021194547.672988-8-matheus.ferst@eldorado.org.br (mailing list archive)
State New, archived
Headers show
Series PowerISA v3.1 instruction batch | expand

Commit Message

Matheus K. Ferst Oct. 21, 2021, 7:45 p.m. UTC
From: Luis Pires <luis.pires@eldorado.org.br>

Implement the following PowerISA v3.1 instruction:
cntlzdm: Count Leading Zeros Doubleword Under Bit Mask

Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
 target/ppc/helper.h                        |  1 +
 target/ppc/insn32.decode                   |  1 +
 target/ppc/int_helper.c                    | 18 ++++++++++++++++++
 target/ppc/translate/fixedpoint-impl.c.inc | 12 ++++++++++++
 4 files changed, 32 insertions(+)

Comments

Richard Henderson Oct. 22, 2021, 11:16 p.m. UTC | #1
On 10/21/21 12:45 PM, matheus.ferst@eldorado.org.br wrote:
> +uint64_t helper_CNTLZDM(uint64_t src, uint64_t mask)
> +{
> +    uint64_t sel_bit, count = 0;
> +
> +    while (mask != 0) {
> +        sel_bit = 0x8000000000000000ULL >> clz64(mask);
> +
> +        if (src & sel_bit) {
> +            break;
> +        }

We need to count how many mask are set left of mask & src.
How about

     sh = clz64(src & mask);
     if (sh == 0) {
         return 0;
     }
     return ctpop64(mask >> (64 - sh));

which could probably be implemented inline relatively easy.

> +static bool trans_CNTLZDM(DisasContext *ctx, arg_X *a)
> +{
> +    REQUIRE_64BIT(ctx);
> +    REQUIRE_INSNS_FLAGS2(ctx, ISA310);
> +#if defined(TARGET_PPC64)
> +    gen_helper_CNTLZDM(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
> +#else
> +    qemu_build_not_reached();
> +#endif
> +    return true;
> +}

Why the ifdef here?  Oh, I see. You could just use target_long in the helper to avoid 
that.  And if not, you should move the helper into an ifdef too.


r~
Matheus K. Ferst Oct. 26, 2021, 2:33 p.m. UTC | #2
On 22/10/2021 20:16, Richard Henderson wrote:
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> 
> On 10/21/21 12:45 PM, matheus.ferst@eldorado.org.br wrote:
>> +uint64_t helper_CNTLZDM(uint64_t src, uint64_t mask)
>> +{
>> +    uint64_t sel_bit, count = 0;
>> +
>> +    while (mask != 0) {
>> +        sel_bit = 0x8000000000000000ULL >> clz64(mask);
>> +
>> +        if (src & sel_bit) {
>> +            break;
>> +        }
> 
> We need to count how many mask are set left of mask & src.
> How about
> 
>      sh = clz64(src & mask);
>      if (sh == 0) {
>          return 0;
>      }
>      return ctpop64(mask >> (64 - sh));
> 
> which could probably be implemented inline relatively easy.
> 

Thanks for this suggestion Richard, we'll try to inline it.

>> +static bool trans_CNTLZDM(DisasContext *ctx, arg_X *a)
>> +{
>> +    REQUIRE_64BIT(ctx);
>> +    REQUIRE_INSNS_FLAGS2(ctx, ISA310);
>> +#if defined(TARGET_PPC64)
>> +    gen_helper_CNTLZDM(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
>> +#else
>> +    qemu_build_not_reached();
>> +#endif
>> +    return true;
>> +}
> 
> Why the ifdef here?  Oh, I see. You could just use target_long in the 
> helper to avoid
> that.  And if not, you should move the helper into an ifdef too.
> 

That's the same case of cfuged. There is a vector version of this 
instruction (vclzdm) that is not 64-bits only (at least on paper), so it 
should receive i64 and cannot be inside an ifdef(TARGET_PPC64). I'll add 
this info to the commit message.

If we dismiss the possibility of a future 32-bits implementation of 
PowerISA v3.1, we can move the helper inside the ifdef and add 
REQUIRE_64BITS in vclzdm/vctzdm (and vcfuged, vpdepd, vpextd, etc.)
diff mbox series

Patch

diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 6fa3e15fe9..ee7c82fb60 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -47,6 +47,7 @@  DEF_HELPER_FLAGS_1(popcntb, TCG_CALL_NO_RWG_SE, tl, tl)
 DEF_HELPER_FLAGS_2(cmpb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
 DEF_HELPER_3(sraw, tl, env, tl, tl)
 DEF_HELPER_FLAGS_2(cfuged, TCG_CALL_NO_RWG_SE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(CNTLZDM, TCG_CALL_NO_RWG_SE, i64, i64, i64)
 #if defined(TARGET_PPC64)
 DEF_HELPER_FLAGS_2(cmpeqb, TCG_CALL_NO_RWG_SE, i32, tl, tl)
 DEF_HELPER_FLAGS_1(popcntw, TCG_CALL_NO_RWG_SE, tl, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 9cb9fc00b8..221cb00dd6 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -203,6 +203,7 @@  ADDPCIS         010011 ..... ..... .......... 00010 .   @DX
 ## Fixed-Point Logical Instructions
 
 CFUGED          011111 ..... ..... ..... 0011011100 -   @X
+CNTLZDM         011111 ..... ..... ..... 0000111011 -   @X
 
 ### Float-Point Load Instructions
 
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index b3d302390a..dcef356034 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -386,6 +386,24 @@  uint64_t helper_cfuged(uint64_t src, uint64_t mask)
     return left | (right >> n);
 }
 
+uint64_t helper_CNTLZDM(uint64_t src, uint64_t mask)
+{
+    uint64_t sel_bit, count = 0;
+
+    while (mask != 0) {
+        sel_bit = 0x8000000000000000ULL >> clz64(mask);
+
+        if (src & sel_bit) {
+            break;
+        }
+
+        count++;
+        mask &= ~sel_bit;
+    }
+
+    return count;
+}
+
 /*****************************************************************************/
 /* PowerPC 601 specific instructions (POWER bridge) */
 target_ulong helper_div(CPUPPCState *env, target_ulong arg1, target_ulong arg2)
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc
index 0a6b3d61d1..814fef2782 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -415,3 +415,15 @@  static bool trans_CFUGED(DisasContext *ctx, arg_X *a)
 #endif
     return true;
 }
+
+static bool trans_CNTLZDM(DisasContext *ctx, arg_X *a)
+{
+    REQUIRE_64BIT(ctx);
+    REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+#if defined(TARGET_PPC64)
+    gen_helper_CNTLZDM(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
+#else
+    qemu_build_not_reached();
+#endif
+    return true;
+}