diff mbox series

[v2,21/32] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4)

Message ID 20211027180730.1551932-22-f4bug@amsat.org (mailing list archive)
State New, archived
Headers show
Series target/mips: Fully convert MSA opcodes to decodetree | expand

Commit Message

Philippe Mathieu-Daudé Oct. 27, 2021, 6:07 p.m. UTC 
Convert 3-register operations to decodetree.

Per the Encoding of Operation Field for 3R Instruction Format'
(Table 3.25), these instructions are not defined for the BYTE
format. Therefore the TRANS_DF_iii_b() macro returns 'false'
in that case, because no such instruction is decoded.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v2: TRANS_DF_iii_b() uses array[4]
---
 target/mips/tcg/msa.decode      |  11 ++
 target/mips/tcg/msa_translate.c | 195 ++++++--------------------------
 2 files changed, 48 insertions(+), 158 deletions(-)

Comments

Richard Henderson Oct. 27, 2021, 10:02 p.m. UTC | #1 
On 10/27/21 11:07 AM, Philippe Mathieu-Daudé wrote:
> Convert 3-register operations to decodetree.
> 
> Per the Encoding of Operation Field for 3R Instruction Format'
> (Table 3.25), these instructions are not defined for the BYTE
> format. Therefore the TRANS_DF_iii_b() macro returns 'false'
> in that case, because no such instruction is decoded.
> 
> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> v2: TRANS_DF_iii_b() uses array[4]
> ---
>   target/mips/tcg/msa.decode      |  11 ++
>   target/mips/tcg/msa_translate.c | 195 ++++++--------------------------
>   2 files changed, 48 insertions(+), 158 deletions(-)
> 
> diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
> index 7201b821ae0..f6471b92fc7 100644
> --- a/target/mips/tcg/msa.decode
> +++ b/target/mips/tcg/msa.decode
> @@ -87,10 +87,21 @@ BNZ                 010001 111 .. ..... ................    @bz
>     SRARI             011110 010 ....... ..... .....  001010  @bit
>     SRLRI             011110 011 ....... ..... .....  001010  @bit
>   
> +  DOTP_S            011110 000.. ..... ..... .....  010011  @3r
> +  DOTP_U            011110 001.. ..... ..... .....  010011  @3r
> +  DPADD_S           011110 010.. ..... ..... .....  010011  @3r
> +  DPADD_U           011110 011.. ..... ..... .....  010011  @3r
> +  DPSUB_S           011110 100.. ..... ..... .....  010011  @3r
> +  DPSUB_U           011110 101.. ..... ..... .....  010011  @3r
> +
>     SLD               011110 000 .. ..... ..... ..... 010100  @3r
>     SPLAT             011110 001 .. ..... ..... ..... 010100  @3r
>   
>     VSHF              011110 000 .. ..... ..... ..... 010101  @3r
> +  HADD_S            011110 100.. ..... ..... .....  010101  @3r
> +  HADD_U            011110 101.. ..... ..... .....  010101  @3r
> +  HSUB_S            011110 110.. ..... ..... .....  010101  @3r
> +  HSUB_U            011110 111.. ..... ..... .....  010101  @3r
>   
>     FCAF              011110 0000 . ..... ..... ..... 011010  @3rf
>     FCUN              011110 0001 . ..... ..... ..... 011010  @3rf
> diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
> index c7ca629d684..5cc704c9ace 100644
> --- a/target/mips/tcg/msa_translate.c
> +++ b/target/mips/tcg/msa_translate.c
> @@ -47,13 +47,11 @@ enum {
>       OPC_ADD_A_df    = (0x0 << 23) | OPC_MSA_3R_10,
>       OPC_SUBS_S_df   = (0x0 << 23) | OPC_MSA_3R_11,
>       OPC_MULV_df     = (0x0 << 23) | OPC_MSA_3R_12,
> -    OPC_DOTP_S_df   = (0x0 << 23) | OPC_MSA_3R_13,
>       OPC_SRA_df      = (0x1 << 23) | OPC_MSA_3R_0D,
>       OPC_SUBV_df     = (0x1 << 23) | OPC_MSA_3R_0E,
>       OPC_ADDS_A_df   = (0x1 << 23) | OPC_MSA_3R_10,
>       OPC_SUBS_U_df   = (0x1 << 23) | OPC_MSA_3R_11,
>       OPC_MADDV_df    = (0x1 << 23) | OPC_MSA_3R_12,
> -    OPC_DOTP_U_df   = (0x1 << 23) | OPC_MSA_3R_13,
>       OPC_SRAR_df     = (0x1 << 23) | OPC_MSA_3R_15,
>       OPC_SRL_df      = (0x2 << 23) | OPC_MSA_3R_0D,
>       OPC_MAX_S_df    = (0x2 << 23) | OPC_MSA_3R_0E,
> @@ -61,7 +59,6 @@ enum {
>       OPC_ADDS_S_df   = (0x2 << 23) | OPC_MSA_3R_10,
>       OPC_SUBSUS_U_df = (0x2 << 23) | OPC_MSA_3R_11,
>       OPC_MSUBV_df    = (0x2 << 23) | OPC_MSA_3R_12,
> -    OPC_DPADD_S_df  = (0x2 << 23) | OPC_MSA_3R_13,
>       OPC_PCKEV_df    = (0x2 << 23) | OPC_MSA_3R_14,
>       OPC_SRLR_df     = (0x2 << 23) | OPC_MSA_3R_15,
>       OPC_BCLR_df     = (0x3 << 23) | OPC_MSA_3R_0D,
> @@ -69,7 +66,6 @@ enum {
>       OPC_CLT_U_df    = (0x3 << 23) | OPC_MSA_3R_0F,
>       OPC_ADDS_U_df   = (0x3 << 23) | OPC_MSA_3R_10,
>       OPC_SUBSUU_S_df = (0x3 << 23) | OPC_MSA_3R_11,
> -    OPC_DPADD_U_df  = (0x3 << 23) | OPC_MSA_3R_13,
>       OPC_PCKOD_df    = (0x3 << 23) | OPC_MSA_3R_14,
>       OPC_BSET_df     = (0x4 << 23) | OPC_MSA_3R_0D,
>       OPC_MIN_S_df    = (0x4 << 23) | OPC_MSA_3R_0E,
> @@ -77,30 +73,24 @@ enum {
>       OPC_AVE_S_df    = (0x4 << 23) | OPC_MSA_3R_10,
>       OPC_ASUB_S_df   = (0x4 << 23) | OPC_MSA_3R_11,
>       OPC_DIV_S_df    = (0x4 << 23) | OPC_MSA_3R_12,
> -    OPC_DPSUB_S_df  = (0x4 << 23) | OPC_MSA_3R_13,
>       OPC_ILVL_df     = (0x4 << 23) | OPC_MSA_3R_14,
> -    OPC_HADD_S_df   = (0x4 << 23) | OPC_MSA_3R_15,
>       OPC_BNEG_df     = (0x5 << 23) | OPC_MSA_3R_0D,
>       OPC_MIN_U_df    = (0x5 << 23) | OPC_MSA_3R_0E,
>       OPC_CLE_U_df    = (0x5 << 23) | OPC_MSA_3R_0F,
>       OPC_AVE_U_df    = (0x5 << 23) | OPC_MSA_3R_10,
>       OPC_ASUB_U_df   = (0x5 << 23) | OPC_MSA_3R_11,
>       OPC_DIV_U_df    = (0x5 << 23) | OPC_MSA_3R_12,
> -    OPC_DPSUB_U_df  = (0x5 << 23) | OPC_MSA_3R_13,
>       OPC_ILVR_df     = (0x5 << 23) | OPC_MSA_3R_14,
> -    OPC_HADD_U_df   = (0x5 << 23) | OPC_MSA_3R_15,
>       OPC_BINSL_df    = (0x6 << 23) | OPC_MSA_3R_0D,
>       OPC_MAX_A_df    = (0x6 << 23) | OPC_MSA_3R_0E,
>       OPC_AVER_S_df   = (0x6 << 23) | OPC_MSA_3R_10,
>       OPC_MOD_S_df    = (0x6 << 23) | OPC_MSA_3R_12,
>       OPC_ILVEV_df    = (0x6 << 23) | OPC_MSA_3R_14,
> -    OPC_HSUB_S_df   = (0x6 << 23) | OPC_MSA_3R_15,
>       OPC_BINSR_df    = (0x7 << 23) | OPC_MSA_3R_0D,
>       OPC_MIN_A_df    = (0x7 << 23) | OPC_MSA_3R_0E,
>       OPC_AVER_U_df   = (0x7 << 23) | OPC_MSA_3R_10,
>       OPC_MOD_U_df    = (0x7 << 23) | OPC_MSA_3R_12,
>       OPC_ILVOD_df    = (0x7 << 23) | OPC_MSA_3R_14,
> -    OPC_HSUB_U_df   = (0x7 << 23) | OPC_MSA_3R_15,
>   
>       /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
>       OPC_SLDI_df     = (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM,
> @@ -257,6 +247,21 @@ typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32);
>   #define TRANS_DF_ii(NAME, trans_func, gen_func) \
>       TRANS_DF_x(ii, NAME, trans_func, gen_func)
>   
> +#define TRANS_DF_iii_b(NAME, trans_func, gen_func) \
> +    static gen_helper_piii * const NAME##_tab[4] = { \
> +        gen_func##_h, gen_func##_w, gen_func##_d \
> +    }; \
> +    static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
> +    { \
> +        if (a->df == DF_BYTE) { \
> +            return false; \
> +        } \
> +        if (!check_msa_enabled(ctx)) { \
> +            return true; \
> +        } \
> +        return trans_func(ctx, a, NAME##_tab[a->df - DF_HALF]); \

Either reduce the size of the array by one, or place the NULL in its proper place at the 
beginning rather than the end of the array.  I think the latter is in the end clearer.

You could just as well place the checks within trans_msa_3r:

     if (gen_msa_3r == NULL) {
         return false;
     }
     if (!check_msa_enabled(ctx)) {
         return true;
     }


r~
Philippe Mathieu-Daudé Oct. 28, 2021, 1:40 p.m. UTC | #2 
On 10/28/21 00:02, Richard Henderson wrote:
> On 10/27/21 11:07 AM, Philippe Mathieu-Daudé wrote:
>> Convert 3-register operations to decodetree.
>>
>> Per the Encoding of Operation Field for 3R Instruction Format'
>> (Table 3.25), these instructions are not defined for the BYTE
>> format. Therefore the TRANS_DF_iii_b() macro returns 'false'
>> in that case, because no such instruction is decoded.
>>
>> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>> ---
>> v2: TRANS_DF_iii_b() uses array[4]
>> ---
>>   target/mips/tcg/msa.decode      |  11 ++
>>   target/mips/tcg/msa_translate.c | 195 ++++++--------------------------
>>   2 files changed, 48 insertions(+), 158 deletions(-)

>>   +#define TRANS_DF_iii_b(NAME, trans_func, gen_func) \
>> +    static gen_helper_piii * const NAME##_tab[4] = { \
>> +        gen_func##_h, gen_func##_w, gen_func##_d \
>> +    }; \
>> +    static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
>> +    { \
>> +        if (a->df == DF_BYTE) { \
>> +            return false; \
>> +        } \
>> +        if (!check_msa_enabled(ctx)) { \
>> +            return true; \
>> +        } \
>> +        return trans_func(ctx, a, NAME##_tab[a->df - DF_HALF]); \
> 
> Either reduce the size of the array by one, or place the NULL in its
> proper place at the beginning rather than the end of the array.  I think
> the latter is in the end clearer.

Yes.

> You could just as well place the checks within trans_msa_3r:
> 
>     if (gen_msa_3r == NULL) {
>         return false;
>     }
>     if (!check_msa_enabled(ctx)) {
>         return true;
>     }

Indeed, thank you.
diff mbox series

Patch

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 7201b821ae0..f6471b92fc7 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -87,10 +87,21 @@  BNZ                 010001 111 .. ..... ................    @bz
   SRARI             011110 010 ....... ..... .....  001010  @bit
   SRLRI             011110 011 ....... ..... .....  001010  @bit
 
+  DOTP_S            011110 000.. ..... ..... .....  010011  @3r
+  DOTP_U            011110 001.. ..... ..... .....  010011  @3r
+  DPADD_S           011110 010.. ..... ..... .....  010011  @3r
+  DPADD_U           011110 011.. ..... ..... .....  010011  @3r
+  DPSUB_S           011110 100.. ..... ..... .....  010011  @3r
+  DPSUB_U           011110 101.. ..... ..... .....  010011  @3r
+
   SLD               011110 000 .. ..... ..... ..... 010100  @3r
   SPLAT             011110 001 .. ..... ..... ..... 010100  @3r
 
   VSHF              011110 000 .. ..... ..... ..... 010101  @3r
+  HADD_S            011110 100.. ..... ..... .....  010101  @3r
+  HADD_U            011110 101.. ..... ..... .....  010101  @3r
+  HSUB_S            011110 110.. ..... ..... .....  010101  @3r
+  HSUB_U            011110 111.. ..... ..... .....  010101  @3r
 
   FCAF              011110 0000 . ..... ..... ..... 011010  @3rf
   FCUN              011110 0001 . ..... ..... ..... 011010  @3rf
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index c7ca629d684..5cc704c9ace 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -47,13 +47,11 @@  enum {
     OPC_ADD_A_df    = (0x0 << 23) | OPC_MSA_3R_10,
     OPC_SUBS_S_df   = (0x0 << 23) | OPC_MSA_3R_11,
     OPC_MULV_df     = (0x0 << 23) | OPC_MSA_3R_12,
-    OPC_DOTP_S_df   = (0x0 << 23) | OPC_MSA_3R_13,
     OPC_SRA_df      = (0x1 << 23) | OPC_MSA_3R_0D,
     OPC_SUBV_df     = (0x1 << 23) | OPC_MSA_3R_0E,
     OPC_ADDS_A_df   = (0x1 << 23) | OPC_MSA_3R_10,
     OPC_SUBS_U_df   = (0x1 << 23) | OPC_MSA_3R_11,
     OPC_MADDV_df    = (0x1 << 23) | OPC_MSA_3R_12,
-    OPC_DOTP_U_df   = (0x1 << 23) | OPC_MSA_3R_13,
     OPC_SRAR_df     = (0x1 << 23) | OPC_MSA_3R_15,
     OPC_SRL_df      = (0x2 << 23) | OPC_MSA_3R_0D,
     OPC_MAX_S_df    = (0x2 << 23) | OPC_MSA_3R_0E,
@@ -61,7 +59,6 @@  enum {
     OPC_ADDS_S_df   = (0x2 << 23) | OPC_MSA_3R_10,
     OPC_SUBSUS_U_df = (0x2 << 23) | OPC_MSA_3R_11,
     OPC_MSUBV_df    = (0x2 << 23) | OPC_MSA_3R_12,
-    OPC_DPADD_S_df  = (0x2 << 23) | OPC_MSA_3R_13,
     OPC_PCKEV_df    = (0x2 << 23) | OPC_MSA_3R_14,
     OPC_SRLR_df     = (0x2 << 23) | OPC_MSA_3R_15,
     OPC_BCLR_df     = (0x3 << 23) | OPC_MSA_3R_0D,
@@ -69,7 +66,6 @@  enum {
     OPC_CLT_U_df    = (0x3 << 23) | OPC_MSA_3R_0F,
     OPC_ADDS_U_df   = (0x3 << 23) | OPC_MSA_3R_10,
     OPC_SUBSUU_S_df = (0x3 << 23) | OPC_MSA_3R_11,
-    OPC_DPADD_U_df  = (0x3 << 23) | OPC_MSA_3R_13,
     OPC_PCKOD_df    = (0x3 << 23) | OPC_MSA_3R_14,
     OPC_BSET_df     = (0x4 << 23) | OPC_MSA_3R_0D,
     OPC_MIN_S_df    = (0x4 << 23) | OPC_MSA_3R_0E,
@@ -77,30 +73,24 @@  enum {
     OPC_AVE_S_df    = (0x4 << 23) | OPC_MSA_3R_10,
     OPC_ASUB_S_df   = (0x4 << 23) | OPC_MSA_3R_11,
     OPC_DIV_S_df    = (0x4 << 23) | OPC_MSA_3R_12,
-    OPC_DPSUB_S_df  = (0x4 << 23) | OPC_MSA_3R_13,
     OPC_ILVL_df     = (0x4 << 23) | OPC_MSA_3R_14,
-    OPC_HADD_S_df   = (0x4 << 23) | OPC_MSA_3R_15,
     OPC_BNEG_df     = (0x5 << 23) | OPC_MSA_3R_0D,
     OPC_MIN_U_df    = (0x5 << 23) | OPC_MSA_3R_0E,
     OPC_CLE_U_df    = (0x5 << 23) | OPC_MSA_3R_0F,
     OPC_AVE_U_df    = (0x5 << 23) | OPC_MSA_3R_10,
     OPC_ASUB_U_df   = (0x5 << 23) | OPC_MSA_3R_11,
     OPC_DIV_U_df    = (0x5 << 23) | OPC_MSA_3R_12,
-    OPC_DPSUB_U_df  = (0x5 << 23) | OPC_MSA_3R_13,
     OPC_ILVR_df     = (0x5 << 23) | OPC_MSA_3R_14,
-    OPC_HADD_U_df   = (0x5 << 23) | OPC_MSA_3R_15,
     OPC_BINSL_df    = (0x6 << 23) | OPC_MSA_3R_0D,
     OPC_MAX_A_df    = (0x6 << 23) | OPC_MSA_3R_0E,
     OPC_AVER_S_df   = (0x6 << 23) | OPC_MSA_3R_10,
     OPC_MOD_S_df    = (0x6 << 23) | OPC_MSA_3R_12,
     OPC_ILVEV_df    = (0x6 << 23) | OPC_MSA_3R_14,
-    OPC_HSUB_S_df   = (0x6 << 23) | OPC_MSA_3R_15,
     OPC_BINSR_df    = (0x7 << 23) | OPC_MSA_3R_0D,
     OPC_MIN_A_df    = (0x7 << 23) | OPC_MSA_3R_0E,
     OPC_AVER_U_df   = (0x7 << 23) | OPC_MSA_3R_10,
     OPC_MOD_U_df    = (0x7 << 23) | OPC_MSA_3R_12,
     OPC_ILVOD_df    = (0x7 << 23) | OPC_MSA_3R_14,
-    OPC_HSUB_U_df   = (0x7 << 23) | OPC_MSA_3R_15,
 
     /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
     OPC_SLDI_df     = (0x0 << 22) | (0x00 << 16) | OPC_MSA_ELM,
@@ -257,6 +247,21 @@  typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32);
 #define TRANS_DF_ii(NAME, trans_func, gen_func) \
     TRANS_DF_x(ii, NAME, trans_func, gen_func)
 
+#define TRANS_DF_iii_b(NAME, trans_func, gen_func) \
+    static gen_helper_piii * const NAME##_tab[4] = { \
+        gen_func##_h, gen_func##_w, gen_func##_d \
+    }; \
+    static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+    { \
+        if (a->df == DF_BYTE) { \
+            return false; \
+        } \
+        if (!check_msa_enabled(ctx)) { \
+            return true; \
+        } \
+        return trans_func(ctx, a, NAME##_tab[a->df - DF_HALF]); \
+    }
+
 static void gen_check_zero_element(TCGv tresult, uint8_t df, uint8_t wt,
                                    TCGCond cond)
 {
@@ -466,10 +471,32 @@  static bool trans_msa_3r_df(DisasContext *ctx, arg_msa_r *a,
     return true;
 }
 
+static bool trans_msa_3r(DisasContext *ctx, arg_msa_r *a,
+                         gen_helper_piii *gen_msa_3r)
+{
+    gen_msa_3r(cpu_env,
+               tcg_constant_i32(a->wd),
+               tcg_constant_i32(a->ws),
+               tcg_constant_i32(a->wt));
+
+    return true;
+}
+
+TRANS_DF_iii_b(DOTP_S,  trans_msa_3r,    gen_helper_msa_dotp_s);
+TRANS_DF_iii_b(DOTP_U,  trans_msa_3r,    gen_helper_msa_dotp_u);
+TRANS_DF_iii_b(DPADD_S, trans_msa_3r,    gen_helper_msa_dpadd_s);
+TRANS_DF_iii_b(DPADD_U, trans_msa_3r,    gen_helper_msa_dpadd_u);
+TRANS_DF_iii_b(DPSUB_S, trans_msa_3r,    gen_helper_msa_dpsub_s);
+TRANS_DF_iii_b(DPSUB_U, trans_msa_3r,    gen_helper_msa_dpsub_u);
+
 TRANS_MSA(SLD,          trans_msa_3r_df, gen_helper_msa_sld_df);
 TRANS_MSA(SPLAT,        trans_msa_3r_df, gen_helper_msa_splat_df);
 
 TRANS_MSA(VSHF,         trans_msa_3r_df, gen_helper_msa_vshf_df);
+TRANS_DF_iii_b(HADD_S,  trans_msa_3r,    gen_helper_msa_hadd_s);
+TRANS_DF_iii_b(HADD_U,  trans_msa_3r,    gen_helper_msa_hadd_u);
+TRANS_DF_iii_b(HSUB_S,  trans_msa_3r,    gen_helper_msa_hsub_s);
+TRANS_DF_iii_b(HSUB_U,  trans_msa_3r,    gen_helper_msa_hsub_u);
 
 static void gen_msa_3r(DisasContext *ctx)
 {
@@ -1285,154 +1312,6 @@  static void gen_msa_3r(DisasContext *ctx)
             break;
         }
         break;
-
-    case OPC_DOTP_S_df:
-    case OPC_DOTP_U_df:
-    case OPC_DPADD_S_df:
-    case OPC_DPADD_U_df:
-    case OPC_DPSUB_S_df:
-    case OPC_HADD_S_df:
-    case OPC_DPSUB_U_df:
-    case OPC_HADD_U_df:
-    case OPC_HSUB_S_df:
-    case OPC_HSUB_U_df:
-        if (df == DF_BYTE) {
-            gen_reserved_instruction(ctx);
-            break;
-        }
-        switch (MASK_MSA_3R(ctx->opcode)) {
-        case OPC_HADD_S_df:
-            switch (df) {
-            case DF_HALF:
-                gen_helper_msa_hadd_s_h(cpu_env, twd, tws, twt);
-                break;
-            case DF_WORD:
-                gen_helper_msa_hadd_s_w(cpu_env, twd, tws, twt);
-                break;
-            case DF_DOUBLE:
-                gen_helper_msa_hadd_s_d(cpu_env, twd, tws, twt);
-                break;
-            }
-            break;
-        case OPC_HADD_U_df:
-            switch (df) {
-            case DF_HALF:
-                gen_helper_msa_hadd_u_h(cpu_env, twd, tws, twt);
-                break;
-            case DF_WORD:
-                gen_helper_msa_hadd_u_w(cpu_env, twd, tws, twt);
-                break;
-            case DF_DOUBLE:
-                gen_helper_msa_hadd_u_d(cpu_env, twd, tws, twt);
-                break;
-            }
-            break;
-        case OPC_HSUB_S_df:
-            switch (df) {
-            case DF_HALF:
-                gen_helper_msa_hsub_s_h(cpu_env, twd, tws, twt);
-                break;
-            case DF_WORD:
-                gen_helper_msa_hsub_s_w(cpu_env, twd, tws, twt);
-                break;
-            case DF_DOUBLE:
-                gen_helper_msa_hsub_s_d(cpu_env, twd, tws, twt);
-                break;
-            }
-            break;
-        case OPC_HSUB_U_df:
-            switch (df) {
-            case DF_HALF:
-                gen_helper_msa_hsub_u_h(cpu_env, twd, tws, twt);
-                break;
-            case DF_WORD:
-                gen_helper_msa_hsub_u_w(cpu_env, twd, tws, twt);
-                break;
-            case DF_DOUBLE:
-                gen_helper_msa_hsub_u_d(cpu_env, twd, tws, twt);
-                break;
-            }
-            break;
-        case OPC_DOTP_S_df:
-            switch (df) {
-            case DF_HALF:
-                gen_helper_msa_dotp_s_h(cpu_env, twd, tws, twt);
-                break;
-            case DF_WORD:
-                gen_helper_msa_dotp_s_w(cpu_env, twd, tws, twt);
-                break;
-            case DF_DOUBLE:
-                gen_helper_msa_dotp_s_d(cpu_env, twd, tws, twt);
-                break;
-            }
-            break;
-        case OPC_DOTP_U_df:
-            switch (df) {
-            case DF_HALF:
-                gen_helper_msa_dotp_u_h(cpu_env, twd, tws, twt);
-                break;
-            case DF_WORD:
-                gen_helper_msa_dotp_u_w(cpu_env, twd, tws, twt);
-                break;
-            case DF_DOUBLE:
-                gen_helper_msa_dotp_u_d(cpu_env, twd, tws, twt);
-                break;
-            }
-            break;
-        case OPC_DPADD_S_df:
-            switch (df) {
-            case DF_HALF:
-                gen_helper_msa_dpadd_s_h(cpu_env, twd, tws, twt);
-                break;
-            case DF_WORD:
-                gen_helper_msa_dpadd_s_w(cpu_env, twd, tws, twt);
-                break;
-            case DF_DOUBLE:
-                gen_helper_msa_dpadd_s_d(cpu_env, twd, tws, twt);
-                break;
-            }
-            break;
-        case OPC_DPADD_U_df:
-            switch (df) {
-            case DF_HALF:
-                gen_helper_msa_dpadd_u_h(cpu_env, twd, tws, twt);
-                break;
-            case DF_WORD:
-                gen_helper_msa_dpadd_u_w(cpu_env, twd, tws, twt);
-                break;
-            case DF_DOUBLE:
-                gen_helper_msa_dpadd_u_d(cpu_env, twd, tws, twt);
-                break;
-            }
-            break;
-        case OPC_DPSUB_S_df:
-            switch (df) {
-            case DF_HALF:
-                gen_helper_msa_dpsub_s_h(cpu_env, twd, tws, twt);
-                break;
-            case DF_WORD:
-                gen_helper_msa_dpsub_s_w(cpu_env, twd, tws, twt);
-                break;
-            case DF_DOUBLE:
-                gen_helper_msa_dpsub_s_d(cpu_env, twd, tws, twt);
-                break;
-            }
-            break;
-        case OPC_DPSUB_U_df:
-            switch (df) {
-            case DF_HALF:
-                gen_helper_msa_dpsub_u_h(cpu_env, twd, tws, twt);
-                break;
-            case DF_WORD:
-                gen_helper_msa_dpsub_u_w(cpu_env, twd, tws, twt);
-                break;
-            case DF_DOUBLE:
-                gen_helper_msa_dpsub_u_d(cpu_env, twd, tws, twt);
-                break;
-            }
-            break;
-        }
-        break;
     default:
         MIPS_INVAL("MSA instruction");
         gen_reserved_instruction(ctx);