[v2,27/32] target/mips: Convert MSA MOVE.V opcode to decodetree

Commit Message

Philippe Mathieu-Daudé Oct. 27, 2021, 6:07 p.m. UTC

Convert the MOVE.V opcode (Vector Move) to decodetree.

Reviewed-by: Jiaxun Yang <[e-mail]>
Reviewed-by: Richard Henderson <[e-mail]>
Signed-off-by: Philippe Mathieu-Daudé <[e-mail]>
---
 target/mips/tcg/msa.decode      |  7 ++++++-
 target/mips/tcg/msa_translate.c | 19 ++++++++++++++-----
 2 files changed, 20 insertions(+), 6 deletions(-)

Patch

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 7c309526444..cfa5fa5d688 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -21,6 +21,7 @@ 
 &msa_ldst           df  wd ws    sa
 &msa_bit            df  wd ws       m
 &msa_elm_df         df  wd ws       n
+&msa_elm                wd ws
 
 %dfn_df             16:6 !function=msa_elm_df
 %dfn_n              16:6 !function=msa_elm_n
@@ -32,6 +33,7 @@ 
 @bz_v               ...... ... ..    wt:5 sa:16             &msa_bz df=3
 @bz                 ...... ...  df:2 wt:5 sa:16             &msa_bz
 @elm_df             ...... .... ......    ws:5 wd:5 ......  &msa_elm_df df=%dfn_df n=%dfn_n
+@elm                ...... ..........     ws:5 wd:5 ......  &msa_elm
 @vec                ...... .....     wt:5 ws:5 wd:5 ......  &msa_r df=0
 @2r                 ...... ........  df:2 ws:5 wd:5 ......  &msa_r wt=0
 @2rf                ...... ......... df:1 ws:5 wd:5 ......  &msa_r wt=0
@@ -165,7 +167,10 @@  BNZ                 010001 111 .. ..... ................    @bz
 
   SLDI              011110 0000 ...... ..... .....  011001  @elm_df
   SPLATI            011110 0001 ...... ..... .....  011001  @elm_df
-  COPY_S            011110 0010 ...... ..... .....  011001  @elm_df
+  {
+    MOVE_V          011110 0010111110  ..... .....  011001  @elm
+    COPY_S          011110 0010 ...... ..... .....  011001  @elm_df
+  }
   COPY_U            011110 0011 ...... ..... .....  011001  @elm_df
   INSERT            011110 0100 ...... ..... .....  011001  @elm_df
   INSVE             011110 0101 ...... ..... .....  011001  @elm_df
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 2ed637f16da..0655b61801b 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -36,7 +36,6 @@  enum {
     /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */
     OPC_CTCMSA      = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM,
     OPC_CFCMSA      = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM,
-    OPC_MOVE_V      = (0x2 << 22) | (0x3E << 16) | OPC_MSA_ELM,
 };
 
 static const char msaregnames[][6] = {
@@ -510,6 +509,19 @@  TRANS_DF_iii_b(HADD_U,  trans_msa_3r,    gen_helper_msa_hadd_u);
 TRANS_DF_iii_b(HSUB_S,  trans_msa_3r,    gen_helper_msa_hsub_s);
 TRANS_DF_iii_b(HSUB_U,  trans_msa_3r,    gen_helper_msa_hsub_u);
 
+static bool trans_MOVE_V(DisasContext *ctx, arg_msa_elm *a)
+{
+    if (!check_msa_enabled(ctx)) {
+        return true;
+    }
+
+    gen_helper_msa_move_v(cpu_env,
+                          tcg_constant_i32(a->wd),
+                          tcg_constant_i32(a->ws));
+
+    return true;
+}
+
 static void gen_msa_elm_3e(DisasContext *ctx)
 {
 #define MASK_MSA_ELM_DF3E(op)   (MASK_MSA_MINOR(op) | (op & (0x3FF << 16)))
@@ -528,9 +540,6 @@  static void gen_msa_elm_3e(DisasContext *ctx)
         gen_helper_msa_cfcmsa(telm, cpu_env, tsr);
         gen_store_gpr(telm, dest);
         break;
-    case OPC_MOVE_V:
-        gen_helper_msa_move_v(cpu_env, tdt, tsr);
-        break;
     default:
         MIPS_INVAL("MSA instruction");
         gen_reserved_instruction(ctx);
@@ -627,7 +636,7 @@  static void gen_msa_elm(DisasContext *ctx)
     uint8_t dfn = (ctx->opcode >> 16) & 0x3f;
 
     if (dfn == 0x3E) {
-        /* CTCMSA, CFCMSA, MOVE.V */
+        /* CTCMSA, CFCMSA */
         gen_msa_elm_3e(ctx);
         return;
     } else {