| Message ID | 20211028044342.3070385-1-alistair.francis@opensource.wdc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 10/27/21 9:43 PM, Alistair Francis wrote: > From: Alistair Francis<alistair.francis@wdc.com> > > The following changes since commit c52d69e7dbaaed0ffdef8125e79218672c30161d: > > Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-20211027' into staging (2021-10-27 11:45:18 -0700) > > are available in the Git repository at: > > git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211028 > > for you to fetch changes up to 344b61e1478c8eb37e81b96f63d8f5071f5a38e1: > > target/riscv: remove force HS exception (2021-10-28 14:39:23 +1000) > > ---------------------------------------------------------------- > Fifth RISC-V PR for QEMU 6.2 > > - Use a shared PLIC config helper function > - Fixup the OpenTitan PLIC configuration > - Add support for the experimental J extension > - Update the fmin/fmax handling > - Fixup VS interrupt forwarding For avoidance of doubt, I'll wait for an ack from Alistair, whether or not he wants to update the two min/max patches to Frank's final version. The code appears to be the same between v4 and v5, but the commit comments are improved, so this is not something that could be fixed with a second patch. r~
From: Alistair Francis <alistair.francis@wdc.com> The following changes since commit c52d69e7dbaaed0ffdef8125e79218672c30161d: Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-20211027' into staging (2021-10-27 11:45:18 -0700) are available in the Git repository at: git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20211028 for you to fetch changes up to 344b61e1478c8eb37e81b96f63d8f5071f5a38e1: target/riscv: remove force HS exception (2021-10-28 14:39:23 +1000) ---------------------------------------------------------------- Fifth RISC-V PR for QEMU 6.2 - Use a shared PLIC config helper function - Fixup the OpenTitan PLIC configuration - Add support for the experimental J extension - Update the fmin/fmax handling - Fixup VS interrupt forwarding ---------------------------------------------------------------- Alexey Baturo (7): target/riscv: Add J-extension into RISC-V target/riscv: Add CSR defines for RISC-V PM extension target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode target/riscv: Add J extension state description target/riscv: Print new PM CSRs in QEMU logs target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions target/riscv: Allow experimental J-ext to be turned on Alistair Francis (6): hw/riscv: virt: Don't use a macro for the PLIC configuration hw/riscv: boot: Add a PLIC config string function hw/riscv: sifive_u: Use the PLIC config helper function hw/riscv: microchip_pfsoc: Use the PLIC config helper function hw/riscv: virt: Use the PLIC config helper function hw/riscv: opentitan: Fixup the PLIC context addresses Anatoly Parshintsev (1): target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension Chih-Min Chao (2): softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin target/riscv: change the api for RVF/RVD fmin/fmax Jose Martins (2): target/riscv: fix VS interrupts forwarding to HS target/riscv: remove force HS exception include/fpu/softfloat.h | 10 ++ include/hw/riscv/boot.h | 2 + include/hw/riscv/microchip_pfsoc.h | 1 - include/hw/riscv/sifive_u.h | 1 - include/hw/riscv/virt.h | 1 - target/riscv/cpu.h | 17 +- target/riscv/cpu_bits.h | 102 +++++++++++- fpu/softfloat.c | 19 ++- hw/riscv/boot.c | 25 +++ hw/riscv/microchip_pfsoc.c | 14 +- hw/riscv/opentitan.c | 4 +- hw/riscv/sifive_u.c | 14 +- hw/riscv/virt.c | 20 +-- target/riscv/cpu.c | 13 ++ target/riscv/cpu_helper.c | 72 +++----- target/riscv/csr.c | 285 ++++++++++++++++++++++++++++++++ target/riscv/fpu_helper.c | 16 +- target/riscv/machine.c | 27 +++ target/riscv/translate.c | 43 +++++ fpu/softfloat-parts.c.inc | 25 ++- target/riscv/insn_trans/trans_rva.c.inc | 3 + target/riscv/insn_trans/trans_rvd.c.inc | 2 + target/riscv/insn_trans/trans_rvf.c.inc | 2 + target/riscv/insn_trans/trans_rvi.c.inc | 2 + 24 files changed, 605 insertions(+), 115 deletions(-)