From patchwork Fri Oct 29 08:58:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Chang X-Patchwork-Id: 12592277 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B677C433EF for ; Fri, 29 Oct 2021 09:31:13 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D8EF860F93 for ; Fri, 29 Oct 2021 09:31:11 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org D8EF860F93 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:36670 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mgOEA-0007YJ-Un for qemu-devel@archiver.kernel.org; Fri, 29 Oct 2021 05:31:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34894) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mgNlA-0005vR-Jr for qemu-devel@nongnu.org; Fri, 29 Oct 2021 05:01:13 -0400 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]:37488) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mgNl8-0005vb-Ct for qemu-devel@nongnu.org; Fri, 29 Oct 2021 05:01:12 -0400 Received: by mail-pg1-x529.google.com with SMTP id s136so9302544pgs.4 for ; Fri, 29 Oct 2021 02:01:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oOj+WAwR3Y+ZbPHLpBezoiGEudJOTaitId1dfFRvKug=; b=E4qUvbeVlVfm84hk252DjIq0pEasKM5Zk7oNYqaTPSmSt5rJiSJ9xZleyZiRIMpbBz 1LthEQ1IKAtaO2blf8MYCZpzFJAwlPXC8WS9U6tuENTxeNh6X0+19oRjsGGa6aeRjaFt iUAI1qGyMys8qFMlEYUse3FsGQYqYRqQnBeW3LQNDj0avJStPPmf1NAEIr3qUehdCkPs 9LRA9f3tTNQr+aIzU6F7Z+fMj/UvrEO73jCAgMGCxonhbLhHQjsXwXc7CvkkHVHkshuK kCz1/rj5bjBEfVThB2rpXmXES7TYN8WFE2AMv6HM8TLxeF5XydxnO7CZBq1/oSUxC+cH zqEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oOj+WAwR3Y+ZbPHLpBezoiGEudJOTaitId1dfFRvKug=; b=ywbiFwE3WyUEbGQ5O9d8WSAcWj348yL49OV9obZiA1JQZ8LCKn2AZb9+avfKzqgGFM BH6BtUtfbnJ4jOn5hMEaPH5ldsBCQd+cbMC+2LU7pmpwK5q8S+ovRBwXktTdtFSBUg4o gblLWCu9HkLdSPxpQss8BarJCwSfRzIAuksTRtoqKSYYYQl34livkB8XGEi+TgmvhwlU lyBmjCG7K5iEhFs4vvR1Wz03rajnHEeXTH5HheNYc/3iwYj3bIMjitMEEQe42b88wCww zKofxq/i+2CUgJCw3BcHgrc9BBzcMTD86QieuaMpei/UqoKt5pdrauwbL99BcVaTKq5Z jNQA== X-Gm-Message-State: AOAM530JTe6SMuG6n+IW2Nzkd/7XYyBaImMd26WWGZDBTgnS2Qgkt/YT gLx5bd7Y6oppCFxs/eIDQzo0CU8CwB31sz6J X-Google-Smtp-Source: ABdhPJy/fqdgXMrWFlvZdy4r72km6zfELOaiEpmm8S2IXl/eMS0j2QAY240KKO+Q2EP9ERueTHjmpw== X-Received: by 2002:a63:4a61:: with SMTP id j33mr6822086pgl.475.1635498069003; Fri, 29 Oct 2021 02:01:09 -0700 (PDT) Received: from localhost.localdomain ([2402:7500:46b:ce55:983b:6962:38ac:e1b9]) by smtp.gmail.com with ESMTPSA id t13sm5081477pgn.94.2021.10.29.02.01.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Oct 2021 02:01:08 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Subject: [PATCH v9 26/76] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation Date: Fri, 29 Oct 2021 16:58:31 +0800 Message-Id: <20211029085922.255197-27-frank.chang@sifive.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211029085922.255197-1-frank.chang@sifive.com> References: <20211029085922.255197-1-frank.chang@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=frank.chang@sifive.com; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Frank Chang , Bin Meng , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang Update vext_get_vlmax() and MAXSZ() to take fractional LMUL into calculation for RVV 1.0. Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 27 ++++++++++++++++--------- target/riscv/cpu_helper.c | 16 ++++++++++++--- target/riscv/insn_trans/trans_rvv.c.inc | 12 ++++++++++- 3 files changed, 42 insertions(+), 13 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 709b7c3abbb..11a0f41b27e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -430,18 +430,27 @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) #endif /* - * A simplification for VLMAX - * = (1 << LMUL) * VLEN / (8 * (1 << SEW)) - * = (VLEN << LMUL) / (8 << SEW) - * = (VLEN << LMUL) >> (SEW + 3) - * = VLEN >> (SEW + 3 - LMUL) + * Encode LMUL to lmul as follows: + * LMUL vlmul lmul + * 1 000 0 + * 2 001 1 + * 4 010 2 + * 8 011 3 + * - 100 - + * 1/8 101 -3 + * 1/4 110 -2 + * 1/2 111 -1 + * + * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) + * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 + * => VLMAX = vlen >> (1 + 3 - (-3)) + * = 256 >> 7 + * = 2 */ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) { - uint8_t sew, lmul; - - sew = FIELD_EX64(vtype, VTYPE, VSEW); - lmul = FIELD_EX64(vtype, VTYPE, VLMUL); + uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); + int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); return cpu->cfg.vlen >> (sew + 3 - lmul); } diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 7149657edf9..cb58b06dfe7 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -75,12 +75,22 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, *cs_base = 0; if (riscv_has_ext(env, RVV)) { + /* + * If env->vl equals to VLMAX, we can use generic vector operation + * expanders (GVEC) to accerlate the vector operations. + * However, as LMUL could be a fractional number. The maximum + * vector size can be operated might be less than 8 bytes, + * which is not supported by GVEC. So we set vl_eq_vlmax flag to true + * only when maxsz >= 8 bytes. + */ uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype); - bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl); + uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW); + uint32_t maxsz = vlmax << sew; + bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl) && + (maxsz >= 8); flags = FIELD_DP32(flags, TB_FLAGS, VILL, FIELD_EX64(env->vtype, VTYPE, VILL)); - flags = FIELD_DP32(flags, TB_FLAGS, SEW, - FIELD_EX64(env->vtype, VTYPE, VSEW)); + flags = FIELD_DP32(flags, TB_FLAGS, SEW, sew); flags = FIELD_DP32(flags, TB_FLAGS, LMUL, FIELD_EX64(env->vtype, VTYPE, VLMUL)); flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax); diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index e12db9aae8b..5c04ac90dae 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1049,7 +1049,17 @@ GEN_LDST_WHOLE_TRANS(vs8r_v, 8, true) /* *** Vector Integer Arithmetic Instructions */ -#define MAXSZ(s) (s->vlen >> (3 - s->lmul)) + +/* + * MAXSZ returns the maximum vector size can be operated in bytes, + * which is used in GVEC IR when vl_eq_vlmax flag is set to true + * to accerlate vector operation. + */ +static inline uint32_t MAXSZ(DisasContext *s) +{ + int scale = s->lmul - 3; + return scale < 0 ? s->vlen >> -scale : s->vlen << scale; +} static bool opivv_check(DisasContext *s, arg_rmrr *a) {