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[v9,33/76] target/riscv: rvv-1.0: element index instruction

Message ID	20211029085922.255197-34-frank.chang@sifive.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=w/R+=PR=nongnu.org=qemu-devel-bounces+qemu-devel=archiver.kernel.org@kernel.org> DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org C08F160FC0 From: frank.chang@sifive.com To: qemu-devel@nongnu.org Subject: [PATCH v9 33/76] target/riscv: rvv-1.0: element index instruction Date: Fri, 29 Oct 2021 16:58:38 +0800 Message-Id: <20211029085922.255197-34-frank.chang@sifive.com> In-Reply-To: <20211029085922.255197-1-frank.chang@sifive.com> References: <20211029085922.255197-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=frank.chang@sifive.com; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Cc: qemu-riscv@nongnu.org, Frank Chang <frank.chang@sifive.com>, Bin Meng <bin.meng@windriver.com>, Richard Henderson <richard.henderson@linaro.org>, Alistair Francis <alistair.francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com> Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org>
Series	support vector extension v1.0 \| expand [v9,00/76] support vector extension v1.0 [v9,01/76] target/riscv: drop vector 0.7.1 and add 1.0 support [v9,02/76] target/riscv: Use FIELD_EX32() to extract wd field [v9,03/76] target/riscv: rvv-1.0: add mstatus VS field [v9,04/76] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty [v9,05/76] target/riscv: rvv-1.0: add sstatus VS field [v9,06/76] target/riscv: rvv-1.0: introduce writable misa.v field [v9,07/76] target/riscv: rvv-1.0: add translation-time vector context status [v9,08/76] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers [v9,09/76] target/riscv: rvv-1.0: add vcsr register [v9,10/76] target/riscv: rvv-1.0: add vlenb register [v9,11/76] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers [v9,12/76] target/riscv: rvv-1.0: remove MLEN calculations [v9,13/76] target/riscv: rvv-1.0: add fractional LMUL [v9,14/76] target/riscv: rvv-1.0: add VMA and VTA [v9,15/76] target/riscv: rvv-1.0: update check functions [v9,16/76] target/riscv: introduce more imm value modes in translator functions [v9,17/76] target/riscv: rvv:1.0: add translation-time nan-box helper function [v9,18/76] target/riscv: rvv-1.0: remove amo operations instructions [v9,19/76] target/riscv: rvv-1.0: configure instructions [v9,20/76] target/riscv: rvv-1.0: stride load and store instructions [v9,21/76] target/riscv: rvv-1.0: index load and store instructions [v9,22/76] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns [v9,23/76] target/riscv: rvv-1.0: fault-only-first unit stride load [v9,24/76] target/riscv: rvv-1.0: load/store whole register instructions [v9,25/76] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns [v9,26/76] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation [v9,27/76] target/riscv: rvv-1.0: floating-point square-root instruction [v9,28/76] target/riscv: rvv-1.0: floating-point classify instructions [v9,29/76] target/riscv: rvv-1.0: count population in mask instruction [v9,30/76] target/riscv: rvv-1.0: find-first-set mask bit instruction [v9,31/76] target/riscv: rvv-1.0: set-X-first mask bit instructions [v9,32/76] target/riscv: rvv-1.0: iota instruction [v9,33/76] target/riscv: rvv-1.0: element index instruction [v9,34/76] target/riscv: rvv-1.0: allow load element with sign-extended [v9,35/76] target/riscv: rvv-1.0: register gather instructions [v9,36/76] target/riscv: rvv-1.0: integer scalar move instructions [v9,37/76] target/riscv: rvv-1.0: floating-point move instruction [v9,38/76] target/riscv: rvv-1.0: floating-point scalar move instructions [v9,39/76] target/riscv: rvv-1.0: whole register move instructions [v9,40/76] target/riscv: rvv-1.0: integer extension instructions [v9,41/76] target/riscv: rvv-1.0: single-width averaging add and subtract instructions [v9,42/76] target/riscv: rvv-1.0: single-width bit shift instructions [v9,43/76] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow [v9,44/76] target/riscv: rvv-1.0: narrowing integer right shift instructions [v9,45/76] target/riscv: rvv-1.0: widening integer multiply-add instructions [v9,46/76] target/riscv: rvv-1.0: single-width saturating add and subtract instructions [v9,47/76] target/riscv: rvv-1.0: integer comparison instructions [v9,48/76] target/riscv: rvv-1.0: floating-point compare instructions [v9,49/76] target/riscv: rvv-1.0: mask-register logical instructions [v9,50/76] target/riscv: rvv-1.0: slide instructions [v9,51/76] target/riscv: rvv-1.0: floating-point slide instructions [v9,52/76] target/riscv: rvv-1.0: narrowing fixed-point clip instructions [v9,53/76] target/riscv: rvv-1.0: single-width floating-point reduction [v9,54/76] target/riscv: rvv-1.0: widening floating-point reduction instructions [v9,55/76] target/riscv: rvv-1.0: single-width scaling shift instructions [v9,56/76] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add [v9,57/76] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf [v9,58/76] target/riscv: rvv-1.0: remove integer extract instruction [v9,59/76] target/riscv: rvv-1.0: floating-point min/max instructions [v9,60/76] target/riscv: introduce floating-point rounding mode enum [v9,61/76] target/riscv: rvv-1.0: floating-point/integer type-convert instructions [v9,62/76] target/riscv: rvv-1.0: widening floating-point/integer type-convert [v9,63/76] target/riscv: add "set round to odd" rounding mode helper function [v9,64/76] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert [v9,65/76] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits [v9,66/76] target/riscv: rvv-1.0: implement vstart CSR [v9,67/76] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid [v9,68/76] target/riscv: gdb: support vector registers for rv64 & rv32 [v9,69/76] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction [v9,70/76] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction [v9,71/76] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 [v9,72/76] target/riscv: rvv-1.0: add vsetivli instruction [v9,73/76] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() [v9,74/76] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns [v9,75/76] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm [v9,76/76] target/riscv: rvv-1.0: update opivv_vadc_check() comment

Commit Message

Frank Chang Oct. 29, 2021, 8:58 a.m. UTC

From: Frank Chang <frank.chang@sifive.com>

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn32.decode | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff mbox series

Patch

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 3ac5162aeb7..ab274dcde12 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -633,7 +633,7 @@  vmsbf_m         010100 . ..... 00001 010 ..... 1010111 @r2_vm
 vmsif_m         010100 . ..... 00011 010 ..... 1010111 @r2_vm
 vmsof_m         010100 . ..... 00010 010 ..... 1010111 @r2_vm
 viota_m         010100 . ..... 10000 010 ..... 1010111 @r2_vm
-vid_v           010110 . 00000 10001 010 ..... 1010111 @r1_vm
+vid_v           010100 . 00000 10001 010 ..... 1010111 @r1_vm
 vext_x_v        001100 1 ..... ..... 010 ..... 1010111 @r
 vmv_s_x         001101 1 00000 ..... 110 ..... 1010111 @r2
 vfmv_f_s        001100 1 ..... 00000 001 ..... 1010111 @r2rd