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Fri, 29 Oct 2021 02:03:43 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Subject: [PATCH v9 65/76] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits Date: Fri, 29 Oct 2021 16:59:10 +0800 Message-Id: <20211029085922.255197-66-frank.chang@sifive.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211029085922.255197-1-frank.chang@sifive.com> References: <20211029085922.255197-1-frank.chang@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Frank Chang , Bin Meng , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- target/riscv/vector_helper.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 11a0f41b27e..5d93ccdfa71 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -100,7 +100,7 @@ typedef struct CPURISCVState CPURISCVState; #include "pmp.h" #endif -#define RV_VLEN_MAX 256 +#define RV_VLEN_MAX 1024 FIELD(VTYPE, VLMUL, 0, 3) FIELD(VTYPE, VSEW, 3, 3) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 42e94491184..be3f9f13275 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -567,8 +567,8 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data, base = get_gpr(s, rs1, EXT_NONE); /* - * As simd_desc supports at most 256 bytes, and in this implementation, - * the max vector group length is 2048 bytes. So split it into two parts. + * As simd_desc supports at most 2048 bytes, and in this implementation, + * the max vector group length is 4096 bytes. So split it into two parts. * * The first part is vlen in bytes, encoded in maxsz of simd_desc. * The second part is lmul, encoded in data of simd_desc. diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index a78f36b4b3b..e61c8731425 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -124,7 +124,7 @@ static inline int32_t vext_lmul(uint32_t desc) static inline uint32_t vext_max_elems(uint32_t desc, uint32_t esz) { /* - * As simd_desc support at most 256 bytes, the max vlen is 256 bits. + * As simd_desc support at most 2048 bytes, the max vlen is 1024 bits. * so vlen in bytes (vlenb) is encoded as maxsz. */ uint32_t vlenb = simd_maxsz(desc);