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Mon, 01 Nov 2021 16:23:59 -0700 (PDT) Date: Mon, 1 Nov 2021 16:23:42 -0700 In-Reply-To: <20211101232346.1070813-1-wuhaotsh@google.com> Message-Id: <20211101232346.1070813-3-wuhaotsh@google.com> Mime-Version: 1.0 References: <20211101232346.1070813-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.33.1.1089.g2158813163f-goog Subject: [PATCH v3 2/6] hw/i2c: Read FIFO during RXF_CTL change in NPCM7XX SMBus From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, wuhaotsh@google.com, venture@google.com, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, hskinnemoen@google.com, Titus Rwantare , Corey Minyard Received-SPF: pass client-ip=2607:f8b0:4864:20::64a; envelope-from=3D3eAYQgKChIECzs6BAzy66y3w.u648w4C-vwDw3565y5C.69y@flex--wuhaotsh.bounces.google.com; helo=mail-pl1-x64a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Originally we read in from SMBus when RXF_STS is cleared. However, the driver clears RXF_STS before setting RXF_CTL, causing the SM bus module to read incorrect amount of bytes in FIFO mode when the number of bytes read changed. This patch fixes this issue. Signed-off-by: Hao Wu Reviewed-by: Titus Rwantare Acked-by: Corey Minyard --- hw/i2c/npcm7xx_smbus.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/i2c/npcm7xx_smbus.c b/hw/i2c/npcm7xx_smbus.c index f18e311556..1435daea94 100644 --- a/hw/i2c/npcm7xx_smbus.c +++ b/hw/i2c/npcm7xx_smbus.c @@ -637,9 +637,6 @@ static void npcm7xx_smbus_write_rxf_sts(NPCM7xxSMBusState *s, uint8_t value) { if (value & NPCM7XX_SMBRXF_STS_RX_THST) { s->rxf_sts &= ~NPCM7XX_SMBRXF_STS_RX_THST; - if (s->status == NPCM7XX_SMBUS_STATUS_RECEIVING) { - npcm7xx_smbus_recv_fifo(s); - } } } @@ -651,6 +648,9 @@ static void npcm7xx_smbus_write_rxf_ctl(NPCM7xxSMBusState *s, uint8_t value) new_ctl = KEEP_OLD_BIT(s->rxf_ctl, new_ctl, NPCM7XX_SMBRXF_CTL_LAST); } s->rxf_ctl = new_ctl; + if (s->status == NPCM7XX_SMBUS_STATUS_RECEIVING) { + npcm7xx_smbus_recv_fifo(s); + } } static uint64_t npcm7xx_smbus_read(void *opaque, hwaddr offset, unsigned size)