| Message ID | 20211101235642.926773-4-danielhb413@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | PMU-EBB support for PPC64 TCG | expand |
On 01/11/2021 20:56, Daniel Henrique Barboza wrote: > The PowerISA v3.1 defines that if the proper bits are set (MMCR0_PMC1CE > for PMC1 and MMCR0_PMCjCE for the remaining PMCs), counter negative > conditions are enabled. This means that if the counter value overflows > (i.e. exceeds 0x80000000) a performance monitor alert will occur. This alert > can trigger an event-based exception (to be implemented in the next patches) > if the MMCR0_EBE bit is set. > > For now, overflowing the counter when the PMC is counting cycles will > just trigger a performance monitor alert. This is done by starting the > overflow timer to expire in the moment the overflow would be occuring. The > timer will call fire_PMC_interrupt() (via cpu_ppc_pmu_timer_cb) which will > trigger the PMU alert and, if the conditions are met, an EBB exception. > > Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> > --- > target/ppc/cpu.h | 2 + > target/ppc/power8-pmu.c | 86 ++++++++++++++++++++++++++++++++++++++++- > 2 files changed, 86 insertions(+), 2 deletions(-) > > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > index 6c4643044b..bf718334a5 100644 > --- a/target/ppc/cpu.h > +++ b/target/ppc/cpu.h > @@ -363,6 +363,8 @@ typedef enum { > #define MMCR0_PMCC PPC_BITMASK(44, 45) /* PMC Control */ > #define MMCR0_FC14 PPC_BIT(58) /* PMC Freeze Counters 1-4 bit */ > #define MMCR0_FC56 PPC_BIT(59) /* PMC Freeze Counters 5-6 bit */ > +#define MMCR0_PMC1CE PPC_BIT(48) /* MMCR0 PMC1 Condition Enabled */ > +#define MMCR0_PMCjCE PPC_BIT(49) /* MMCR0 PMCj Condition Enabled */ > /* MMCR0 userspace r/w mask */ > #define MMCR0_UREG_MASK (MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE) > /* MMCR2 userspace r/w mask */ > diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c > index a0a42b666c..fdc94d40b2 100644 > --- a/target/ppc/power8-pmu.c > +++ b/target/ppc/power8-pmu.c > @@ -23,6 +23,8 @@ > > #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) > > +#define COUNTER_NEGATIVE_VAL 0x80000000 > + Since this value will be compared to some env->spr (that is target_ulong), it's probably a good idea to define it as unsigned. Also, you could prefix the name to indicate that it's PMU related, e.g.: #defne PMC_COUNTER_NEGATIVE_VAL 0x80000000UL > /* > * For PMCs 1-4, IBM POWER chips has support for an implementation > * dependent event, 0x1E, that enables cycle counting. The Linux kernel > @@ -93,6 +95,15 @@ static bool pmc_is_active(CPUPPCState *env, int sprn) > return !(env->spr[SPR_POWER_MMCR0] & MMCR0_FC56); > } > > +static bool pmc_has_overflow_enabled(CPUPPCState *env, int sprn) > +{ > + if (sprn == SPR_POWER_PMC1) { > + return env->spr[SPR_POWER_MMCR0] & MMCR0_PMC1CE; > + } > + > + return env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE; > +} > + > static void pmu_update_cycles(CPUPPCState *env) > { > uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); > @@ -121,6 +132,63 @@ static void pmu_update_cycles(CPUPPCState *env) > } > } > > +static void pmu_delete_timers(CPUPPCState *env) > +{ > + int i; > + > + for (i = 0; i < PMU_TIMERS_NUM; i++) { > + timer_del(env->pmu_cyc_overflow_timers[i]); > + } > +} > + > +/* > + * Helper function to retrieve the cycle overflow timer of the > + * 'sprn' counter. Given that PMC5 doesn't have a timer, the > + * amount of timers is less than the total counters and the PMC6 > + * timer is the last of the array. > + */ > +static QEMUTimer *get_cyc_overflow_timer(CPUPPCState *env, int sprn) > +{ > + if (sprn == SPR_POWER_PMC5) { > + return NULL; > + } > + > + if (sprn == SPR_POWER_PMC6) { > + return env->pmu_cyc_overflow_timers[PMU_TIMERS_NUM - 1]; > + } > + > + return env->pmu_cyc_overflow_timers[sprn - SPR_POWER_PMC1]; > +} > + > +static void pmu_start_overflow_timers(CPUPPCState *env) > +{ > + uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); > + int64_t timeout; > + int sprn; > + > + env->pmu_base_time = now; > + > + /* > + * Scroll through all PMCs ad start counter overflow timers for s/ad/and/ > + * PM_CYC events, if needed. > + */ > + for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC6; sprn++) { > + if (!pmc_is_active(env, sprn) || > + !(getPMUEventType(env, sprn) == PMU_EVENT_CYCLES) || > + !pmc_has_overflow_enabled(env, sprn)) { > + continue; > + } > + > + if (env->spr[sprn] >= COUNTER_NEGATIVE_VAL) { > + timeout = 0; > + } else { > + timeout = COUNTER_NEGATIVE_VAL - env->spr[sprn]; extra space between timeout and = ... > + } > + > + timer_mod(get_cyc_overflow_timer(env, sprn), now + timeout); but maybe you can just use timer_mod_anticipate? > + } > +} > + > /* > * A cycle count session consists of the basic operations we > * need to do to support PM_CYC events: redefine a new base_time > @@ -128,8 +196,22 @@ static void pmu_update_cycles(CPUPPCState *env) > */ > static void start_cycle_count_session(CPUPPCState *env) > { > - /* Just define pmu_base_time for now */ > - env->pmu_base_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); > + bool overflow_enabled = env->spr[SPR_POWER_MMCR0] & > + (MMCR0_PMC1CE | MMCR0_PMCjCE); > + > + /* > + * Always delete existing overflow timers when starting a > + * new cycle counting session. > + */ > + pmu_delete_timers(env); > + > + if (!overflow_enabled) { > + /* Define pmu_base_time and leave */ > + env->pmu_base_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); > + return; > + } > + > + pmu_start_overflow_timers(env); > } > > void helper_store_mmcr0(CPUPPCState *env, target_ulong value) > -- > 2.31.1 >
On 11/5/21 09:56, Matheus K. Ferst wrote: > On 01/11/2021 20:56, Daniel Henrique Barboza wrote: >> The PowerISA v3.1 defines that if the proper bits are set (MMCR0_PMC1CE >> for PMC1 and MMCR0_PMCjCE for the remaining PMCs), counter negative >> conditions are enabled. This means that if the counter value overflows >> (i.e. exceeds 0x80000000) a performance monitor alert will occur. This alert >> can trigger an event-based exception (to be implemented in the next patches) >> if the MMCR0_EBE bit is set. >> >> For now, overflowing the counter when the PMC is counting cycles will >> just trigger a performance monitor alert. This is done by starting the >> overflow timer to expire in the moment the overflow would be occuring. The >> timer will call fire_PMC_interrupt() (via cpu_ppc_pmu_timer_cb) which will >> trigger the PMU alert and, if the conditions are met, an EBB exception. >> >> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> >> --- >> target/ppc/cpu.h | 2 + >> target/ppc/power8-pmu.c | 86 ++++++++++++++++++++++++++++++++++++++++- >> 2 files changed, 86 insertions(+), 2 deletions(-) >> >> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h >> index 6c4643044b..bf718334a5 100644 >> --- a/target/ppc/cpu.h >> +++ b/target/ppc/cpu.h >> @@ -363,6 +363,8 @@ typedef enum { >> #define MMCR0_PMCC PPC_BITMASK(44, 45) /* PMC Control */ >> #define MMCR0_FC14 PPC_BIT(58) /* PMC Freeze Counters 1-4 bit */ >> #define MMCR0_FC56 PPC_BIT(59) /* PMC Freeze Counters 5-6 bit */ >> +#define MMCR0_PMC1CE PPC_BIT(48) /* MMCR0 PMC1 Condition Enabled */ >> +#define MMCR0_PMCjCE PPC_BIT(49) /* MMCR0 PMCj Condition Enabled */ >> /* MMCR0 userspace r/w mask */ >> #define MMCR0_UREG_MASK (MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE) >> /* MMCR2 userspace r/w mask */ >> diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c >> index a0a42b666c..fdc94d40b2 100644 >> --- a/target/ppc/power8-pmu.c >> +++ b/target/ppc/power8-pmu.c >> @@ -23,6 +23,8 @@ >> >> #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) >> >> +#define COUNTER_NEGATIVE_VAL 0x80000000 >> + > > Since this value will be compared to some env->spr (that is target_ulong), it's probably a good idea to define it as unsigned. Also, you could prefix the name to indicate that it's PMU related, e.g.: > > #defne PMC_COUNTER_NEGATIVE_VAL 0x80000000UL > >> /* >> * For PMCs 1-4, IBM POWER chips has support for an implementation >> * dependent event, 0x1E, that enables cycle counting. The Linux kernel >> @@ -93,6 +95,15 @@ static bool pmc_is_active(CPUPPCState *env, int sprn) >> return !(env->spr[SPR_POWER_MMCR0] & MMCR0_FC56); >> } >> >> +static bool pmc_has_overflow_enabled(CPUPPCState *env, int sprn) >> +{ >> + if (sprn == SPR_POWER_PMC1) { >> + return env->spr[SPR_POWER_MMCR0] & MMCR0_PMC1CE; >> + } >> + >> + return env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE; >> +} >> + >> static void pmu_update_cycles(CPUPPCState *env) >> { >> uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); >> @@ -121,6 +132,63 @@ static void pmu_update_cycles(CPUPPCState *env) >> } >> } >> >> +static void pmu_delete_timers(CPUPPCState *env) >> +{ >> + int i; >> + >> + for (i = 0; i < PMU_TIMERS_NUM; i++) { >> + timer_del(env->pmu_cyc_overflow_timers[i]); >> + } >> +} >> + >> +/* >> + * Helper function to retrieve the cycle overflow timer of the >> + * 'sprn' counter. Given that PMC5 doesn't have a timer, the >> + * amount of timers is less than the total counters and the PMC6 >> + * timer is the last of the array. >> + */ >> +static QEMUTimer *get_cyc_overflow_timer(CPUPPCState *env, int sprn) >> +{ >> + if (sprn == SPR_POWER_PMC5) { >> + return NULL; >> + } >> + >> + if (sprn == SPR_POWER_PMC6) { >> + return env->pmu_cyc_overflow_timers[PMU_TIMERS_NUM - 1]; >> + } >> + >> + return env->pmu_cyc_overflow_timers[sprn - SPR_POWER_PMC1]; >> +} >> + >> +static void pmu_start_overflow_timers(CPUPPCState *env) >> +{ >> + uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); >> + int64_t timeout; >> + int sprn; >> + >> + env->pmu_base_time = now; >> + >> + /* >> + * Scroll through all PMCs ad start counter overflow timers for > > s/ad/and/ > >> + * PM_CYC events, if needed. >> + */ >> + for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC6; sprn++) { >> + if (!pmc_is_active(env, sprn) || >> + !(getPMUEventType(env, sprn) == PMU_EVENT_CYCLES) || >> + !pmc_has_overflow_enabled(env, sprn)) { >> + continue; >> + } >> + >> + if (env->spr[sprn] >= COUNTER_NEGATIVE_VAL) { >> + timeout = 0; >> + } else { >> + timeout = COUNTER_NEGATIVE_VAL - env->spr[sprn]; > > extra space between timeout and = ... > >> + } >> + >> + timer_mod(get_cyc_overflow_timer(env, sprn), now + timeout); > > but maybe you can just use timer_mod_anticipate? timer_mod_anticipate will not make any difference here because, at this point, we're guaranteed to not have any overflow timer running for the counter. pmu_start_overflow_timers() will always be executed after pmu_delete_timers(), both inside start_cycle_counter_session(). Thanks, Daniel > >> + } >> +} >> + >> /* >> * A cycle count session consists of the basic operations we >> * need to do to support PM_CYC events: redefine a new base_time >> @@ -128,8 +196,22 @@ static void pmu_update_cycles(CPUPPCState *env) >> */ >> static void start_cycle_count_session(CPUPPCState *env) >> { >> - /* Just define pmu_base_time for now */ >> - env->pmu_base_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); >> + bool overflow_enabled = env->spr[SPR_POWER_MMCR0] & >> + (MMCR0_PMC1CE | MMCR0_PMCjCE); >> + >> + /* >> + * Always delete existing overflow timers when starting a >> + * new cycle counting session. >> + */ >> + pmu_delete_timers(env); >> + >> + if (!overflow_enabled) { >> + /* Define pmu_base_time and leave */ >> + env->pmu_base_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); >> + return; >> + } >> + >> + pmu_start_overflow_timers(env); >> } >> >> void helper_store_mmcr0(CPUPPCState *env, target_ulong value) >> -- >> 2.31.1 >>
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 6c4643044b..bf718334a5 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -363,6 +363,8 @@ typedef enum { #define MMCR0_PMCC PPC_BITMASK(44, 45) /* PMC Control */ #define MMCR0_FC14 PPC_BIT(58) /* PMC Freeze Counters 1-4 bit */ #define MMCR0_FC56 PPC_BIT(59) /* PMC Freeze Counters 5-6 bit */ +#define MMCR0_PMC1CE PPC_BIT(48) /* MMCR0 PMC1 Condition Enabled */ +#define MMCR0_PMCjCE PPC_BIT(49) /* MMCR0 PMCj Condition Enabled */ /* MMCR0 userspace r/w mask */ #define MMCR0_UREG_MASK (MMCR0_FC | MMCR0_PMAO | MMCR0_PMAE) /* MMCR2 userspace r/w mask */ diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index a0a42b666c..fdc94d40b2 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -23,6 +23,8 @@ #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) +#define COUNTER_NEGATIVE_VAL 0x80000000 + /* * For PMCs 1-4, IBM POWER chips has support for an implementation * dependent event, 0x1E, that enables cycle counting. The Linux kernel @@ -93,6 +95,15 @@ static bool pmc_is_active(CPUPPCState *env, int sprn) return !(env->spr[SPR_POWER_MMCR0] & MMCR0_FC56); } +static bool pmc_has_overflow_enabled(CPUPPCState *env, int sprn) +{ + if (sprn == SPR_POWER_PMC1) { + return env->spr[SPR_POWER_MMCR0] & MMCR0_PMC1CE; + } + + return env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE; +} + static void pmu_update_cycles(CPUPPCState *env) { uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); @@ -121,6 +132,63 @@ static void pmu_update_cycles(CPUPPCState *env) } } +static void pmu_delete_timers(CPUPPCState *env) +{ + int i; + + for (i = 0; i < PMU_TIMERS_NUM; i++) { + timer_del(env->pmu_cyc_overflow_timers[i]); + } +} + +/* + * Helper function to retrieve the cycle overflow timer of the + * 'sprn' counter. Given that PMC5 doesn't have a timer, the + * amount of timers is less than the total counters and the PMC6 + * timer is the last of the array. + */ +static QEMUTimer *get_cyc_overflow_timer(CPUPPCState *env, int sprn) +{ + if (sprn == SPR_POWER_PMC5) { + return NULL; + } + + if (sprn == SPR_POWER_PMC6) { + return env->pmu_cyc_overflow_timers[PMU_TIMERS_NUM - 1]; + } + + return env->pmu_cyc_overflow_timers[sprn - SPR_POWER_PMC1]; +} + +static void pmu_start_overflow_timers(CPUPPCState *env) +{ + uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + int64_t timeout; + int sprn; + + env->pmu_base_time = now; + + /* + * Scroll through all PMCs ad start counter overflow timers for + * PM_CYC events, if needed. + */ + for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC6; sprn++) { + if (!pmc_is_active(env, sprn) || + !(getPMUEventType(env, sprn) == PMU_EVENT_CYCLES) || + !pmc_has_overflow_enabled(env, sprn)) { + continue; + } + + if (env->spr[sprn] >= COUNTER_NEGATIVE_VAL) { + timeout = 0; + } else { + timeout = COUNTER_NEGATIVE_VAL - env->spr[sprn]; + } + + timer_mod(get_cyc_overflow_timer(env, sprn), now + timeout); + } +} + /* * A cycle count session consists of the basic operations we * need to do to support PM_CYC events: redefine a new base_time @@ -128,8 +196,22 @@ static void pmu_update_cycles(CPUPPCState *env) */ static void start_cycle_count_session(CPUPPCState *env) { - /* Just define pmu_base_time for now */ - env->pmu_base_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + bool overflow_enabled = env->spr[SPR_POWER_MMCR0] & + (MMCR0_PMC1CE | MMCR0_PMCjCE); + + /* + * Always delete existing overflow timers when starting a + * new cycle counting session. + */ + pmu_delete_timers(env); + + if (!overflow_enabled) { + /* Define pmu_base_time and leave */ + env->pmu_base_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + return; + } + + pmu_start_overflow_timers(env); } void helper_store_mmcr0(CPUPPCState *env, target_ulong value)
The PowerISA v3.1 defines that if the proper bits are set (MMCR0_PMC1CE for PMC1 and MMCR0_PMCjCE for the remaining PMCs), counter negative conditions are enabled. This means that if the counter value overflows (i.e. exceeds 0x80000000) a performance monitor alert will occur. This alert can trigger an event-based exception (to be implemented in the next patches) if the MMCR0_EBE bit is set. For now, overflowing the counter when the PMC is counting cycles will just trigger a performance monitor alert. This is done by starting the overflow timer to expire in the moment the overflow would be occuring. The timer will call fire_PMC_interrupt() (via cpu_ppc_pmu_timer_cb) which will trigger the PMU alert and, if the conditions are met, an EBB exception. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> --- target/ppc/cpu.h | 2 + target/ppc/power8-pmu.c | 86 ++++++++++++++++++++++++++++++++++++++++- 2 files changed, 86 insertions(+), 2 deletions(-)