diff mbox series

[RFC,1/6] target/riscv: rvk: add flag support for Zbk[bcx]

Message ID 20211102031128.17296-2-liweiwei@iscas.ac.cn (mailing list archive)
State New, archived
Headers show
Series support subsets of scalar crypto extension | expand

Commit Message

Weiwei Li Nov. 2, 2021, 3:11 a.m. UTC 
Signed-off-by: liweiwei <liweiwei@iscas.ac.cn>
Signed-off-by: wangjunqiang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/cpu.c | 9 ++++++---
 target/riscv/cpu.h | 3 +++
 2 files changed, 9 insertions(+), 3 deletions(-)

Comments

Richard Henderson Nov. 2, 2021, 2:18 p.m. UTC | #1 
On 11/1/21 11:11 PM, liweiwei wrote:
> +++ b/target/riscv/cpu.c
> @@ -472,15 +472,15 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>               error_setg(errp,
>                          "I and E extensions are incompatible");
>                          return;
> -       }
> +        }
>   
>           if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
>               error_setg(errp,
>                          "Either I or E extension must be set");
>                          return;
> -       }
> +        }
>   
> -       if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
> +        if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
>                                  cpu->cfg.ext_a & cpu->cfg.ext_f &
>                                  cpu->cfg.ext_d)) {
>               warn_report("Setting G will also set IMAFD");

This re-indentation should not be happening.


> +    DEFINE_PROP_BOOL("x-zbkb", RISCVCPU, cfg.ext_zbkb, false),
> +    DEFINE_PROP_BOOL("x-zbkc", RISCVCPU, cfg.ext_zbkc, false),
> +    DEFINE_PROP_BOOL("x-zbkx", RISCVCPU, cfg.ext_zbkx, false),

The properties cannot be exposed until the end.

>          bool ext_zbb;
>          bool ext_zbc;
>          bool ext_zbs;
> +        bool ext_zbkb;
> +        bool ext_zbkc;
> +        bool ext_zbkx;

Better to keep them alphabetical: zbk* < zbs.


r~
Weiwei Li Nov. 2, 2021, 3 p.m. UTC | #2 
在 2021/11/2 下午10:18, Richard Henderson 写道:
> On 11/1/21 11:11 PM, liweiwei wrote:
>> +++ b/target/riscv/cpu.c
>> @@ -472,15 +472,15 @@ static void riscv_cpu_realize(DeviceState *dev, 
>> Error **errp)
>>               error_setg(errp,
>>                          "I and E extensions are incompatible");
>>                          return;
>> -       }
>> +        }
>>             if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
>>               error_setg(errp,
>>                          "Either I or E extension must be set");
>>                          return;
>> -       }
>> +        }
>>   -       if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
>> +        if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
>>                                  cpu->cfg.ext_a & cpu->cfg.ext_f &
>>                                  cpu->cfg.ext_d)) {
>>               warn_report("Setting G will also set IMAFD");
>
> This re-indentation should not be happening.
>
Thanks for your comments. I'll restore them later. By the way, the 
reason I changed these is that they don't align with other code.
>> +    DEFINE_PROP_BOOL("x-zbkb", RISCVCPU, cfg.ext_zbkb, false),
>> +    DEFINE_PROP_BOOL("x-zbkc", RISCVCPU, cfg.ext_zbkc, false),
>> +    DEFINE_PROP_BOOL("x-zbkx", RISCVCPU, cfg.ext_zbkx, false),
>
> The properties cannot be exposed until the end.
>
Ok. I'll move these to the end of the patchset.
>>          bool ext_zbb;
>>          bool ext_zbc;
>>          bool ext_zbs;
>> +        bool ext_zbkb;
>> +        bool ext_zbkc;
>> +        bool ext_zbkx;
>
> Better to keep them alphabetical: zbk* < zbs.
>
Ok. I'll move them before zbs.
>
> r~
diff mbox series

Patch

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7d53125dbc..0f03d3efba 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -472,15 +472,15 @@  static void riscv_cpu_realize(DeviceState *dev, Error **errp)
             error_setg(errp,
                        "I and E extensions are incompatible");
                        return;
-       }
+        }
 
         if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
             error_setg(errp,
                        "Either I or E extension must be set");
                        return;
-       }
+        }
 
-       if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
+        if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
                                cpu->cfg.ext_a & cpu->cfg.ext_f &
                                cpu->cfg.ext_d)) {
             warn_report("Setting G will also set IMAFD");
@@ -639,6 +639,9 @@  static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false),
     DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false),
     DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false),
+    DEFINE_PROP_BOOL("x-zbkb", RISCVCPU, cfg.ext_zbkb, false),
+    DEFINE_PROP_BOOL("x-zbkc", RISCVCPU, cfg.ext_zbkc, false),
+    DEFINE_PROP_BOOL("x-zbkx", RISCVCPU, cfg.ext_zbkx, false),
     DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
     DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false),
     DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0760c0af93..f9f4437efc 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -309,6 +309,9 @@  struct RISCVCPU {
         bool ext_zbb;
         bool ext_zbc;
         bool ext_zbs;
+        bool ext_zbkb;
+        bool ext_zbkc;
+        bool ext_zbkx;
         bool ext_counters;
         bool ext_ifencei;
         bool ext_icsr;