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[50.253.99.174]) by smtp.gmail.com with ESMTPSA id h14sm205427ils.75.2021.11.02.15.53.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Nov 2021 15:53:37 -0700 (PDT) From: Warner Losh To: qemu-devel@nongnu.org Subject: [PATCH v2 17/30] bsd-user/arm/target_arch_elf.h: arm get_hwcap2 impl Date: Tue, 2 Nov 2021 16:52:35 -0600 Message-Id: <20211102225248.52999-18-imp@bsdimp.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211102225248.52999-1-imp@bsdimp.com> References: <20211102225248.52999-1-imp@bsdimp.com> MIME-Version: 1.0 Received-SPF: none client-ip=2607:f8b0:4864:20::d2e; envelope-from=imp@bsdimp.com; helo=mail-io1-xd2e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-trivial@nongnu.org, Kyle Evans , Richard Henderson , Philippe Mathieu-Daude , Laurent Vivier , Michael Tokarev , Warner Losh Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Implement the extended HW capabilities for HWCAP2. Signed-off-by: Kyle Evans Signed-off-by: Warner Losh Reviewed-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/arm/target_arch_elf.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/bsd-user/arm/target_arch_elf.h b/bsd-user/arm/target_arch_elf.h index 02d25b8926..4a0215d02e 100644 --- a/bsd-user/arm/target_arch_elf.h +++ b/bsd-user/arm/target_arch_elf.h @@ -32,6 +32,7 @@ #define ELF_EXEC_PAGESIZE 4096 #define ELF_HWCAP get_elf_hwcap() +#define ELF_HWCAP2 get_elf_hwcap2() #define GET_FEATURE(feat, hwcap) \ do { if (arm_feature(&cpu->env, feat)) { hwcaps |= hwcap; } } while (0) @@ -64,6 +65,14 @@ enum { ARM_HWCAP_ARM_EVTSTRM = 1 << 21, }; +enum { + ARM_HWCAP2_ARM_AES = 1 << 0, + ARM_HWCAP2_ARM_PMULL = 1 << 1, + ARM_HWCAP2_ARM_SHA1 = 1 << 2, + ARM_HWCAP2_ARM_SHA2 = 1 << 3, + ARM_HWCAP2_ARM_CRC32 = 1 << 4, +}; + static uint32_t get_elf_hwcap(void) { ARMCPU *cpu = ARM_CPU(thread_cpu); @@ -100,6 +109,19 @@ static uint32_t get_elf_hwcap(void) return hwcaps; } +static uint32_t get_elf_hwcap2(void) +{ + ARMCPU *cpu = ARM_CPU(thread_cpu); + uint32_t hwcaps = 0; + + GET_FEATURE_ID(aa32_aes, ARM_HWCAP2_ARM_AES); + GET_FEATURE_ID(aa32_pmull, ARM_HWCAP2_ARM_PMULL); + GET_FEATURE_ID(aa32_sha1, ARM_HWCAP2_ARM_SHA1); + GET_FEATURE_ID(aa32_sha2, ARM_HWCAP2_ARM_SHA2); + GET_FEATURE_ID(aa32_crc32, ARM_HWCAP2_ARM_CRC32); + return hwcaps; +} + #undef GET_FEATURE #undef GET_FEATURE_ID