From patchwork Fri Nov 12 14:14:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Matheus K. Ferst" X-Patchwork-Id: 12616837 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 246A9C4332F for ; Fri, 12 Nov 2021 14:18:32 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DD03260C4A for ; Fri, 12 Nov 2021 14:18:31 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org DD03260C4A Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=eldorado.org.br Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=nongnu.org Received: from localhost ([::1]:49820 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mlXNu-0000hj-Qn for qemu-devel@archiver.kernel.org; Fri, 12 Nov 2021 09:18:30 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45382) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mlXKi-0006DK-98; Fri, 12 Nov 2021 09:15:15 -0500 Received: from [201.28.113.2] (port=37434 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mlXKg-0007oL-8a; Fri, 12 Nov 2021 09:15:12 -0500 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Fri, 12 Nov 2021 11:14:51 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by power9a (Postfix) with ESMTP id 56276800E9B; Fri, 12 Nov 2021 11:14:51 -0300 (-03) From: matheus.ferst@eldorado.org.br To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v2 3/3] target/ppc: Implement Vector Mask Move insns Date: Fri, 12 Nov 2021 11:14:30 -0300 Message-Id: <20211112141430.631732-4-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211112141430.631732-1-matheus.ferst@eldorado.org.br> References: <20211112141430.631732-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 X-OriginalArrivalTime: 12 Nov 2021 14:14:51.0734 (UTC) FILETIME=[A8963F60:01D7D7CF] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass client-ip=201.28.113.2; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, PDS_HP_HELO_NORDNS=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: danielhb413@gmail.com, richard.henderson@linaro.org, groug@kaod.org, clg@kaod.org, Matheus Ferst , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Matheus Ferst Implement the following PowerISA v3.1 instructions: mtvsrbm: Move to VSR Byte Mask mtvsrhm: Move to VSR Halfword Mask mtvsrwm: Move to VSR Word Mask mtvsrdm: Move to VSR Doubleword Mask mtvsrqm: Move to VSR Quadword Mask mtvsrbmi: Move to VSR Byte Mask Immediate Suggested-by: Richard Henderson Signed-off-by: Matheus Ferst Reviewed-by: Richard Henderson --- v2: - Applied rth suggestions to do_mtvsrm and trans_MTVSRBMI --- target/ppc/insn32.decode | 11 +++ target/ppc/translate/vmx-impl.c.inc | 115 ++++++++++++++++++++++++++++ 2 files changed, 126 insertions(+) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 639ac22bf0..f68931f4f3 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -40,6 +40,10 @@ %ds_rtp 22:4 !function=times_2 @DS_rtp ...... ....0 ra:5 .............. .. &D rt=%ds_rtp si=%ds_si +&DX_b vrt b +%dx_b 6:10 16:5 0:1 +@DX_b ...... vrt:5 ..... .......... ..... . &DX_b b=%dx_b + &DX rt d %dx_d 6:s10 16:5 0:1 @DX ...... rt:5 ..... .......... ..... . &DX d=%dx_d @@ -413,6 +417,13 @@ VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN ## Vector Mask Manipulation Instructions +MTVSRBM 000100 ..... 10000 ..... 11001000010 @VX_tb +MTVSRHM 000100 ..... 10001 ..... 11001000010 @VX_tb +MTVSRWM 000100 ..... 10010 ..... 11001000010 @VX_tb +MTVSRDM 000100 ..... 10011 ..... 11001000010 @VX_tb +MTVSRQM 000100 ..... 10100 ..... 11001000010 @VX_tb +MTVSRBMI 000100 ..... ..... .......... 01010 . @DX_b + VEXPANDBM 000100 ..... 00000 ..... 11001000010 @VX_tb VEXPANDHM 000100 ..... 00001 ..... 11001000010 @VX_tb VEXPANDWM 000100 ..... 00010 ..... 11001000010 @VX_tb diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc index dd7337c2f2..404767e4ec 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -1599,6 +1599,121 @@ static bool trans_VEXTRACTQM(DisasContext *ctx, arg_VX_tb *a) return true; } +static bool do_mtvsrm(DisasContext *ctx, arg_VX_tb *a, unsigned vece) +{ + const uint64_t elem_width = 8 << vece, elem_count_half = 8 >> vece; + uint64_t c; + int i, j; + TCGv_i64 hi, lo, t0, t1; + + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + REQUIRE_VECTOR(ctx); + + hi = tcg_temp_new_i64(); + lo = tcg_temp_new_i64(); + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + + tcg_gen_extu_tl_i64(t0, cpu_gpr[a->vrb]); + tcg_gen_extract_i64(hi, t0, elem_count_half, elem_count_half); + tcg_gen_extract_i64(lo, t0, 0, elem_count_half); + + /* + * Spread the bits into their respective elements. + * E.g. for bytes: + * 00000000000000000000000000000000000000000000000000000000abcdefgh + * << 32 - 4 + * 0000000000000000000000000000abcdefgh0000000000000000000000000000 + * | + * 0000000000000000000000000000abcdefgh00000000000000000000abcdefgh + * << 16 - 2 + * 00000000000000abcdefgh00000000000000000000abcdefgh00000000000000 + * | + * 00000000000000abcdefgh000000abcdefgh000000abcdefgh000000abcdefgh + * << 8 - 1 + * 0000000abcdefgh000000abcdefgh000000abcdefgh000000abcdefgh0000000 + * | + * 0000000abcdefgXbcdefgXbcdefgXbcdefgXbcdefgXbcdefgXbcdefgXbcdefgh + * & dup(1) + * 0000000a0000000b0000000c0000000d0000000e0000000f0000000g0000000h + * * 0xff + * aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh + */ + for (i = elem_count_half / 2, j = 32; i > 0; i >>= 1, j >>= 1) { + tcg_gen_shli_i64(t0, hi, j - i); + tcg_gen_shli_i64(t1, lo, j - i); + tcg_gen_or_i64(hi, hi, t0); + tcg_gen_or_i64(lo, lo, t1); + } + + c = dup_const(vece, 1); + tcg_gen_andi_i64(hi, hi, c); + tcg_gen_andi_i64(lo, lo, c); + + c = MAKE_64BIT_MASK(0, elem_width); + tcg_gen_muli_i64(hi, hi, c); + tcg_gen_muli_i64(lo, lo, c); + + set_avr64(a->vrt, lo, false); + set_avr64(a->vrt, hi, true); + + tcg_temp_free_i64(hi); + tcg_temp_free_i64(lo); + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + + return true; +} + +TRANS(MTVSRBM, do_mtvsrm, MO_8) +TRANS(MTVSRHM, do_mtvsrm, MO_16) +TRANS(MTVSRWM, do_mtvsrm, MO_32) +TRANS(MTVSRDM, do_mtvsrm, MO_64) + +static bool trans_MTVSRQM(DisasContext *ctx, arg_VX_tb *a) +{ + TCGv_i64 tmp; + + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + REQUIRE_VECTOR(ctx); + + tmp = tcg_temp_new_i64(); + + tcg_gen_ext_tl_i64(tmp, cpu_gpr[a->vrb]); + tcg_gen_sextract_i64(tmp, tmp, 0, 1); + set_avr64(a->vrt, tmp, false); + set_avr64(a->vrt, tmp, true); + + tcg_temp_free_i64(tmp); + + return true; +} + +static bool trans_MTVSRBMI(DisasContext *ctx, arg_DX_b *a) +{ + const uint64_t mask = dup_const(MO_8, 1); + uint64_t hi, lo; + + REQUIRE_INSNS_FLAGS2(ctx, ISA310); + REQUIRE_VECTOR(ctx); + + hi = extract16(a->b, 8, 8); + lo = extract16(a->b, 0, 8); + + for (int i = 4, j = 32; i > 0; i >>= 1, j >>= 1) { + hi |= hi << (j - i); + lo |= lo << (j - i); + } + + hi = (hi & mask) * 0xFF; + lo = (lo & mask) * 0xFF; + + set_avr64(a->vrt, tcg_constant_i64(hi), true); + set_avr64(a->vrt, tcg_constant_i64(lo), false); + + return true; +} + #define GEN_VAFORM_PAIRED(name0, name1, opc2) \ static void glue(gen_, name0##_##name1)(DisasContext *ctx) \ { \