From patchwork Thu Nov 25 15:08:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 12639335 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9EB53C433F5 for ; Thu, 25 Nov 2021 15:13:41 +0000 (UTC) Received: from localhost ([::1]:52230 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mqGRQ-0002TW-OL for qemu-devel@archiver.kernel.org; Thu, 25 Nov 2021 10:13:40 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37354) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mqGMf-00036L-9r; Thu, 25 Nov 2021 10:08:45 -0500 Received: from [2607:f8b0:4864:20::933] (port=45933 helo=mail-ua1-x933.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mqGMc-000222-O8; Thu, 25 Nov 2021 10:08:45 -0500 Received: by mail-ua1-x933.google.com with SMTP id ay21so12881763uab.12; Thu, 25 Nov 2021 07:08:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WiBgOYsCCyrj24xlUrZfxtYyn1qT8pceu1C4TQlPVeE=; b=QWZw1xofejv+wS6aUDL6XGvEVWMcd1jEO8sKlABfYsn/+OCD95xUpYkU9YQ3bq/qPs ABe2ICCuNsYPcCvTjcPqR9oM/pn7BLWwYB00GFbbRUHPdyvv1geOB9V2GB+6v1acnVz6 fJlshz1strqzm6dlt/p1RjKThxQJ6SnLKnwY0jliqhun2d4cohBqyM/uOoCtBYBG+6g9 6OHPdUJGlnZoj0bezZUTF4yHbcCP2QTXKS7etnvzNuZFCNQ8F/EyiTqAbiauHVFnABvh zX+6FvYjDgh6Kc9ug+jLFuEp6KLcWFE4z+0nSDeEV6vUhhKj9WgRInusc/9Ul5pOnR3A XK4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WiBgOYsCCyrj24xlUrZfxtYyn1qT8pceu1C4TQlPVeE=; b=nc5gjHsQ7Ijui/LDpzuRGB5yt1HbMizXcYdyHxh6/UWSD39CGMY7g3vpE6nUQSEDw6 BN1cq9axCmCVXA7RaO3N0cofYr4JPK5shBvjY7II9fYKWMK6nM51bTEz+6956Ca12YhN FRQ05VGtcfP31kh/+8PbFTJO7g/jcpoHlhJ1ZAWSQHiA5bODFQgHt0lBUN5Krg7Ni07u F5dQwuuf1xkn9iYldz1bw4YAdKnEGeeG503tbxrZAsRiir8SwvhUQqYPywNRUepX6rWt kKSy2IzbkGEr5jwLh0wgwrbxLJexvv6swR3kcwSfqVdCrwEleByWE7GJnHlawX3DzOq7 TDQQ== X-Gm-Message-State: AOAM533Be60a3zFReTHujOAzrZ9X9I2x/1FXy2cL6Aw/mxDgMiuj+eM9 wpo7IVezQvm8uQMb7LlAHJN9WaaJu1g= X-Google-Smtp-Source: ABdhPJwQ/2e4sYHmIfTxAq5rd2NwFT0XX7mCoRhi1+fmpZJ58QrW/l+62T2mel5zb/Y+bpgySPFEtA== X-Received: by 2002:a67:d80c:: with SMTP id e12mr10337500vsj.18.1637852920404; Thu, 25 Nov 2021 07:08:40 -0800 (PST) Received: from rekt.ibmuc.com ([191.19.215.188]) by smtp.gmail.com with ESMTPSA id i27sm2081057uab.8.2021.11.25.07.08.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Nov 2021 07:08:40 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v8 06/10] target/ppc: enable PMU instruction count Date: Thu, 25 Nov 2021 12:08:13 -0300 Message-Id: <20211125150817.573204-7-danielhb413@gmail.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211125150817.573204-1-danielhb413@gmail.com> References: <20211125150817.573204-1-danielhb413@gmail.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::933 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::933; envelope-from=danielhb413@gmail.com; helo=mail-ua1-x933.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The PMU is already counting cycles by calculating time elapsed in nanoseconds. Counting instructions is a different matter and requires another approach. This patch adds the capability of counting completed instructions (Perf event PM_INST_CMPL) by counting the amount of instructions translated in each translation block right before exiting it. A new pmu_count_insns() helper in translation.c was added to do that. After verifying that the PMU is running (MMCR0_FC bit not set), call helper_insns_inc(). This new helper from power8-pmu.c will add the instructions to the relevant counters. It'll also be responsible for triggering counter negative overflows as it is already being done with cycles. Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu.h | 1 + target/ppc/helper.h | 1 + target/ppc/helper_regs.c | 4 +++ target/ppc/power8-pmu-regs.c.inc | 6 +++++ target/ppc/power8-pmu.c | 38 ++++++++++++++++++++++++++ target/ppc/translate.c | 46 ++++++++++++++++++++++++++++++++ 6 files changed, 96 insertions(+) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 9b41b022e2..38cd2b5c43 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -656,6 +656,7 @@ enum { HFLAGS_PR = 14, /* MSR_PR */ HFLAGS_PMCC0 = 15, /* MMCR0 PMCC bit 0 */ HFLAGS_PMCC1 = 16, /* MMCR0 PMCC bit 1 */ + HFLAGS_MMCR0FC = 17, /* MMCR0 FC bit */ HFLAGS_VSX = 23, /* MSR_VSX if cpu has VSX */ HFLAGS_VR = 25, /* MSR_VR if cpu has VRE */ diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 94b4690375..d8a23e054a 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -24,6 +24,7 @@ DEF_HELPER_2(store_mmcr0, void, env, tl) DEF_HELPER_2(store_mmcr1, void, env, tl) DEF_HELPER_3(store_pmc, void, env, i32, i64) DEF_HELPER_2(read_pmc, tl, env, i32) +DEF_HELPER_2(insns_inc, void, env, i32) #endif DEF_HELPER_1(check_tlb_flush_local, void, env) DEF_HELPER_1(check_tlb_flush_global, void, env) diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 99562edd57..875c2fdfc6 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -115,6 +115,10 @@ static uint32_t hreg_compute_hflags_value(CPUPPCState *env) if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCC1) { hflags |= 1 << HFLAGS_PMCC1; } + if (env->spr[SPR_POWER_MMCR0] & MMCR0_FC) { + hflags |= 1 << HFLAGS_MMCR0FC; + } + #ifndef CONFIG_USER_ONLY if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) { diff --git a/target/ppc/power8-pmu-regs.c.inc b/target/ppc/power8-pmu-regs.c.inc index 25b13ad564..580e4e41b2 100644 --- a/target/ppc/power8-pmu-regs.c.inc +++ b/target/ppc/power8-pmu-regs.c.inc @@ -113,6 +113,12 @@ static void write_MMCR0_common(DisasContext *ctx, TCGv val) */ gen_icount_io_start(ctx); gen_helper_store_mmcr0(cpu_env, val); + + /* + * End the translation block because MMCR0 writes can change + * ctx->pmu_frozen. + */ + ctx->base.is_jmp = DISAS_EXIT_UPDATE; } void spr_write_MMCR0_ureg(DisasContext *ctx, int sprn, int gprn) diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index 01e0b9b8fc..59d0def79d 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -112,6 +112,30 @@ static PMUEventType pmc_get_event(CPUPPCState *env, int sprn) return evt_type; } +static bool pmu_increment_insns(CPUPPCState *env, uint32_t num_insns) +{ + bool overflow_triggered = false; + int sprn; + + /* PMC6 never counts instructions */ + for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC5; sprn++) { + if (pmc_get_event(env, sprn) != PMU_EVENT_INSTRUCTIONS) { + continue; + } + + env->spr[sprn] += num_insns; + + if (env->spr[sprn] >= PMC_COUNTER_NEGATIVE_VAL && + pmc_has_overflow_enabled(env, sprn)) { + + overflow_triggered = true; + env->spr[sprn] = PMC_COUNTER_NEGATIVE_VAL; + } + } + + return overflow_triggered; +} + static void pmu_update_cycles(CPUPPCState *env) { uint64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); @@ -258,6 +282,20 @@ static void fire_PMC_interrupt(PowerPCCPU *cpu) return; } +/* This helper assumes that the PMC is running. */ +void helper_insns_inc(CPUPPCState *env, uint32_t num_insns) +{ + bool overflow_triggered; + PowerPCCPU *cpu; + + overflow_triggered = pmu_increment_insns(env, num_insns); + + if (overflow_triggered) { + cpu = env_archcpu(env); + fire_PMC_interrupt(cpu); + } +} + static void cpu_ppc_pmu_timer_cb(void *opaque) { PowerPCCPU *cpu = opaque; diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 9960df6e18..ccc83d0603 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -177,6 +177,7 @@ struct DisasContext { bool hr; bool mmcr0_pmcc0; bool mmcr0_pmcc1; + bool pmu_frozen; ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ int singlestep_enabled; uint32_t flags; @@ -4170,6 +4171,31 @@ static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) #endif } +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) +static void pmu_count_insns(DisasContext *ctx) +{ + /* Do not bother calling the helper if the PMU is frozen */ + if (ctx->pmu_frozen) { + return; + } + + /* + * The PMU insns_inc() helper stops the internal PMU timer if a + * counter overflows happens. In that case, if the guest is + * running with icount and we do not handle it beforehand, + * the helper can trigger a 'bad icount read'. + */ + gen_icount_io_start(ctx); + + gen_helper_insns_inc(cpu_env, tcg_constant_i32(ctx->base.num_insns)); +} +#else +static void pmu_count_insns(DisasContext *ctx) +{ + return; +} +#endif + static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) { return translator_use_goto_tb(&ctx->base, dest); @@ -4180,6 +4206,14 @@ static void gen_lookup_and_goto_ptr(DisasContext *ctx) if (unlikely(ctx->singlestep_enabled)) { gen_debug_exception(ctx); } else { + /* + * tcg_gen_lookup_and_goto_ptr will exit the TB if + * CF_NO_GOTO_PTR is set. Count insns now. + */ + if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { + pmu_count_insns(ctx); + } + tcg_gen_lookup_and_goto_ptr(); } } @@ -4191,6 +4225,7 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) dest = (uint32_t) dest; } if (use_goto_tb(ctx, dest)) { + pmu_count_insns(ctx); tcg_gen_goto_tb(n); tcg_gen_movi_tl(cpu_nip, dest & ~3); tcg_gen_exit_tb(ctx->base.tb, n); @@ -8458,6 +8493,7 @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->hr = (hflags >> HFLAGS_HR) & 1; ctx->mmcr0_pmcc0 = (hflags >> HFLAGS_PMCC0) & 1; ctx->mmcr0_pmcc1 = (hflags >> HFLAGS_PMCC1) & 1; + ctx->pmu_frozen = (hflags >> HFLAGS_MMCR0FC) & 1; ctx->singlestep_enabled = 0; if ((hflags >> HFLAGS_SE) & 1) { @@ -8564,6 +8600,7 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) switch (is_jmp) { case DISAS_TOO_MANY: if (use_goto_tb(ctx, nip)) { + pmu_count_insns(ctx); tcg_gen_goto_tb(0); gen_update_nip(ctx, nip); tcg_gen_exit_tb(ctx->base.tb, 0); @@ -8574,6 +8611,14 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) gen_update_nip(ctx, nip); /* fall through */ case DISAS_CHAIN: + /* + * tcg_gen_lookup_and_goto_ptr will exit the TB if + * CF_NO_GOTO_PTR is set. Count insns now. + */ + if (ctx->base.tb->flags & CF_NO_GOTO_PTR) { + pmu_count_insns(ctx); + } + tcg_gen_lookup_and_goto_ptr(); break; @@ -8581,6 +8626,7 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) gen_update_nip(ctx, nip); /* fall through */ case DISAS_EXIT: + pmu_count_insns(ctx); tcg_gen_exit_tb(NULL, 0); break;