From patchwork Mon Nov 29 03:02:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Chang X-Patchwork-Id: 12643307 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4E431C433F5 for ; Mon, 29 Nov 2021 03:06:11 +0000 (UTC) Received: from localhost ([::1]:50310 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mrWza-0003mb-7k for qemu-devel@archiver.kernel.org; Sun, 28 Nov 2021 22:06:10 -0500 Received: from eggs.gnu.org ([209.51.188.92]:43286) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mrWxc-0000Ts-EU for qemu-devel@nongnu.org; Sun, 28 Nov 2021 22:04:08 -0500 Received: from [2607:f8b0:4864:20::52c] (port=36646 helo=mail-pg1-x52c.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mrWxa-0008N1-2l for qemu-devel@nongnu.org; Sun, 28 Nov 2021 22:04:07 -0500 Received: by mail-pg1-x52c.google.com with SMTP id 137so7426700pgg.3 for ; Sun, 28 Nov 2021 19:04:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UToNhrOkdLW/O50mnkSNHsTzkmzprqfEOkoEklS/wLk=; b=SFzYI19JtQ057ioLvci5cJ1RaX/sJOpM7iDmgm53Zv3ng5mJqfVL39kD/Zs6mfQPhh kwhRBkwNbUZUPGg/uan0xrrqKtRdqdEdeSigC0eFPgrxos6AxbeeaE/uqVo/JnlFC1sD crGtLO/r2uo6+Qc53APzHhj/bFTJuNsvYvnH17cplEYWpq0s7ZR+CYQK67YJsRM0vwjp /vPa09AsSYiwOzlAQQq2CxFlC60DY6pL68P8rwb0nX9m9yuSGRbkRto7araWbU5iOd+H v30bhv6ck6CcbJPfBD9Gnfkk+6MuOJHt5iMBRI99KkCtBPL/0Hw9/kg57qvb7O1MFLF4 MG3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UToNhrOkdLW/O50mnkSNHsTzkmzprqfEOkoEklS/wLk=; b=O35I9Ab88AYT7ta+buXXiY03zFndIU8Jl0uY4i5r3gtePvyifKVpOWcnqo6JHIh+Ef qWgVgBz9Xd+9RzqBjBrBtBNWAxX8CJf/4rB0iFJxXrN5i9V0yaTOKTydIhZ8YD/qyAvj 1dhBY25lHNZBUtQuDxkZE2lhK9p4IqA659Jm3VvM8r2+Js95MByvZuoBa+sEBLenFf0j zmS38atMGgPgyJSwPMiBvUp9gL8jb59RW/Q2XSKCPdltOfiuFKXcG6nujvr5gpSK2zWP Vcz0SkSfHjw/PIsqLFO5LFYcIeaQ1ZOAiNBwnmVPaD+PknpYIy180CEo3RAySnqiiw5C QVvw== X-Gm-Message-State: AOAM533pfhFXgfVlCmfGzhapJM5OT22G/010cGcBiQ8TZqJoeXEj384E 5nGoboMQXwcez++HEupT/jQlASwS3yOihlGr X-Google-Smtp-Source: ABdhPJyeZ7yNQtq5qu/aMgvcIs1CB1TyOTuC4ReLwaCiUKpw2Iy88JScsJGgikcYo4SRs+v57mzCSQ== X-Received: by 2002:a63:2245:: with SMTP id t5mr33107761pgm.436.1638155042692; Sun, 28 Nov 2021 19:04:02 -0800 (PST) Received: from frankchang-ThinkPad-T490.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id oj11sm17904040pjb.46.2021.11.28.19.04.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Nov 2021 19:04:02 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Subject: [PATCH v10 03/77] target/riscv: rvv-1.0: add mstatus VS field Date: Mon, 29 Nov 2021 11:02:23 +0800 Message-Id: <20211129030340.429689-4-frank.chang@sifive.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211129030340.429689-1-frank.chang@sifive.com> References: <20211129030340.429689-1-frank.chang@sifive.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::52c (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=frank.chang@sifive.com; helo=mail-pg1-x52c.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Frank Chang , Bin Meng , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: LIU Zhiwei Signed-off-by: LIU Zhiwei Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 20 +++++++++++++++++++- target/riscv/csr.c | 12 +++++++++++- 4 files changed, 33 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5ea2004ae02..48b8f612109 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -352,6 +352,7 @@ int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); bool riscv_cpu_fp_enabled(CPURISCVState *env); +bool riscv_cpu_vector_enabled(CPURISCVState *env); bool riscv_cpu_virt_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); bool riscv_cpu_two_stage_lookup(int mmu_idx); @@ -395,6 +396,7 @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); #define TB_FLAGS_PRIV_MMU_MASK 3 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) #define TB_FLAGS_MSTATUS_FS MSTATUS_FS +#define TB_FLAGS_MSTATUS_VS MSTATUS_VS typedef CPURISCVState CPUArchState; typedef RISCVCPU ArchCPU; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 9913fa9f778..72a716c9990 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -375,6 +375,7 @@ #define MSTATUS_UBE 0x00000040 #define MSTATUS_MPIE 0x00000080 #define MSTATUS_SPP 0x00000100 +#define MSTATUS_VS 0x00000600 #define MSTATUS_MPP 0x00001800 #define MSTATUS_FS 0x00006000 #define MSTATUS_XS 0x00018000 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f30ff672f8c..5789c2e9690 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -90,12 +90,17 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, #ifdef CONFIG_USER_ONLY flags |= TB_FLAGS_MSTATUS_FS; + flags |= TB_FLAGS_MSTATUS_VS; #else flags |= cpu_mmu_index(env, 0); if (riscv_cpu_fp_enabled(env)) { flags |= env->mstatus & MSTATUS_FS; } + if (riscv_cpu_vector_enabled(env)) { + flags |= env->mstatus & MSTATUS_VS; + } + if (riscv_has_ext(env, RVH)) { if (env->priv == PRV_M || (env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) || @@ -189,11 +194,24 @@ bool riscv_cpu_fp_enabled(CPURISCVState *env) return false; } +/* Return true is vector support is currently enabled */ +bool riscv_cpu_vector_enabled(CPURISCVState *env) +{ + if (env->mstatus & MSTATUS_VS) { + if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_VS)) { + return false; + } + return true; + } + + return false; +} + void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) { uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | - MSTATUS64_UXL; + MSTATUS64_UXL | MSTATUS_VS; bool current_virt = riscv_cpu_virt_enabled(env); g_assert(riscv_has_ext(env, RVH)); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9f41954894d..9b5bd5d7b49 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -273,6 +273,7 @@ static RISCVException write_fcsr(CPURISCVState *env, int csrno, { #if !defined(CONFIG_USER_ONLY) env->mstatus |= MSTATUS_FS; + env->mstatus |= MSTATUS_VS; #endif env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; if (vs(env, csrno) >= 0) { @@ -307,6 +308,9 @@ static RISCVException read_vxrm(CPURISCVState *env, int csrno, static RISCVException write_vxrm(CPURISCVState *env, int csrno, target_ulong val) { +#if !defined(CONFIG_USER_ONLY) + env->mstatus |= MSTATUS_VS; +#endif env->vxrm = val; return RISCV_EXCP_NONE; } @@ -321,6 +325,9 @@ static RISCVException read_vxsat(CPURISCVState *env, int csrno, static RISCVException write_vxsat(CPURISCVState *env, int csrno, target_ulong val) { +#if !defined(CONFIG_USER_ONLY) + env->mstatus |= MSTATUS_VS; +#endif env->vxsat = val; return RISCV_EXCP_NONE; } @@ -335,6 +342,9 @@ static RISCVException read_vstart(CPURISCVState *env, int csrno, static RISCVException write_vstart(CPURISCVState *env, int csrno, target_ulong val) { +#if !defined(CONFIG_USER_ONLY) + env->mstatus |= MSTATUS_VS; +#endif env->vstart = val; return RISCV_EXCP_NONE; } @@ -535,7 +545,7 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | - MSTATUS_TW; + MSTATUS_TW | MSTATUS_VS; if (riscv_cpu_mxl(env) != MXL_RV32) { /*