From patchwork Mon Nov 29 03:03:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Chang X-Patchwork-Id: 12643563 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A5458C433EF for ; Mon, 29 Nov 2021 03:54:32 +0000 (UTC) Received: from localhost ([::1]:50260 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mrXkN-0001cc-KC for qemu-devel@archiver.kernel.org; Sun, 28 Nov 2021 22:54:31 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46120) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mrX3F-0005LU-G5 for qemu-devel@nongnu.org; Sun, 28 Nov 2021 22:09:57 -0500 Received: from [2607:f8b0:4864:20::1035] (port=55000 helo=mail-pj1-x1035.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mrX3D-0000v3-Bc for qemu-devel@nongnu.org; Sun, 28 Nov 2021 22:09:57 -0500 Received: by mail-pj1-x1035.google.com with SMTP id np3so11504236pjb.4 for ; Sun, 28 Nov 2021 19:09:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hn0ncRCJZVbZJu1XmZ/jRBYhcM3muFA/hZLb6BTuMzc=; b=Y/a6gNm/D7YgRhmBGl5n8ZrEUeyHrqfzllScMjZvq/PTZxh/ROeoWAyQ7zrAPJfenG ylJgoEmIuGVN5QHcE2elTbHe7Rw0W9zbdAfoPozn/LLLgakIMZC7v2LyoMntoBRvmCMe OoSjQrOA7Of87Wl80I9JDgY7S/SI9n6OhN/OHQ0inFbJragVCXS2JCUioh3/7egWBX8K TTsLfqfgNQnqBd0IgF91OsXjaW4VLKseIuiQ6xOq3f6U17KUlJGLSKGIr6FsJglr38NO UGBjINRJUJEaTd3bcq+t0DsZsQAU74C3ywtFrdRfjZ3DW/bzcw9dgIeIojwqdH7OSacp GnKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hn0ncRCJZVbZJu1XmZ/jRBYhcM3muFA/hZLb6BTuMzc=; b=cfAP7UgMZu8R11kNytUwfpvU9PmVamXzeFSaewdT+sYvlZpYrDF8xwLU4Pdb0y2B/k Wvyk1nDleobTmD8pyF1k+nOAfABkhPaFyp7ThdwTPQYEtx5bw83E0SjcY1nyHni7O+pv +IgOj2HBxmT8YMRJr9v8nlqWZxXUtj36g7KLH60bTg14n0IC6hI3h14gTxpMNSHr9ugm sqRs/fbCEvidpRtDMk7cq2fR3xfEOXqjMDzbLT+TVBJnvq6eOJq3++awxENOLTzv+VQ/ 2gsRT0APxro9CwWFbCUcKXa6RYeRZlK3ltpJPuegYHYeY/Jrr3c1hSrnRK0Ac4SK+ixC BtxQ== X-Gm-Message-State: AOAM532FTZkDIWc2A7XuEixKF317zoSXTmHw995SfgFPRoUOouv0Y5m6 1NoROLd3/ffh50nBJDKhJLxWz0qGGivvTGkV X-Google-Smtp-Source: ABdhPJz6M6eWLVuFIah6Bre7gcSW9QCYNeiqckZlTlC2o4g5vP609qDzeQMoJN1/eyl2pejblN4zBw== X-Received: by 2002:a17:90a:7e0d:: with SMTP id i13mr35021858pjl.171.1638155393963; Sun, 28 Nov 2021 19:09:53 -0800 (PST) Received: from frankchang-ThinkPad-T490.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id oj11sm17904040pjb.46.2021.11.28.19.09.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Nov 2021 19:09:53 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Subject: [PATCH v10 67/77] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid Date: Mon, 29 Nov 2021 11:03:27 +0800 Message-Id: <20211129030340.429689-68-frank.chang@sifive.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211129030340.429689-1-frank.chang@sifive.com> References: <20211129030340.429689-1-frank.chang@sifive.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1035 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1035.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Frank Chang , Bin Meng , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang If the frm field contains an invalid rounding mode (101-111), attempting to execute any vector floating-point instruction, even those that do not depend on the rounding mode, will raise an illegal instruction exception. Call gen_set_rm() with DYN rounding mode to check and trigger illegal instruction exception if frm field contains invalid value at run-time for vector floating-point instructions. Signed-off-by: Frank Chang Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 7589c8ce32a..53c8573f117 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2374,6 +2374,10 @@ static bool do_opfv(DisasContext *s, arg_rmr *a, int rm) { if (checkfn(s, a)) { + if (rm != RISCV_FRM_DYN) { + gen_set_rm(s, RISCV_FRM_DYN); + } + uint32_t data = 0; TCGLabel *over = gen_new_label(); gen_set_rm(s, rm); @@ -2459,6 +2463,8 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a) require_rvf(s) && vext_check_isa_ill(s) && require_align(a->rd, s->lmul)) { + gen_set_rm(s, RISCV_FRM_DYN); + TCGv_i64 t1; if (s->vl_eq_vlmax) { @@ -2540,6 +2546,10 @@ static bool opfv_widen_check(DisasContext *s, arg_rmr *a) static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ { \ if (opfv_widen_check(s, a)) { \ + if (FRM != RISCV_FRM_DYN) { \ + gen_set_rm(s, RISCV_FRM_DYN); \ + } \ + \ uint32_t data = 0; \ static gen_helper_gvec_3_ptr * const fns[2] = { \ gen_helper_##HELPER##_h, \ @@ -2627,6 +2637,10 @@ static bool opfv_narrow_check(DisasContext *s, arg_rmr *a) static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ { \ if (opfv_narrow_check(s, a)) { \ + if (FRM != RISCV_FRM_DYN) { \ + gen_set_rm(s, RISCV_FRM_DYN); \ + } \ + \ uint32_t data = 0; \ static gen_helper_gvec_3_ptr * const fns[2] = { \ gen_helper_##HELPER##_h, \ @@ -2668,6 +2682,10 @@ static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a) static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ { \ if (opxfv_narrow_check(s, a)) { \ + if (FRM != RISCV_FRM_DYN) { \ + gen_set_rm(s, RISCV_FRM_DYN); \ + } \ + \ uint32_t data = 0; \ static gen_helper_gvec_3_ptr * const fns[3] = { \ gen_helper_##HELPER##_b, \ @@ -3138,6 +3156,8 @@ static bool trans_vfmv_f_s(DisasContext *s, arg_vfmv_f_s *a) if (require_rvv(s) && require_rvf(s) && vext_check_isa_ill(s)) { + gen_set_rm(s, RISCV_FRM_DYN); + unsigned int ofs = (8 << s->sew); unsigned int len = 64 - ofs; TCGv_i64 t_nan; @@ -3162,6 +3182,8 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a) if (require_rvv(s) && require_rvf(s) && vext_check_isa_ill(s)) { + gen_set_rm(s, RISCV_FRM_DYN); + /* The instructions ignore LMUL and vector register group. */ TCGv_i64 t1; TCGLabel *over = gen_new_label();