| Message ID | 20211202144235.1276352-4-clg@kaod.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ppc/pnv: Add support for user created PHB3/PHB4 devices | expand |
On 12/2/21 11:42, Cédric Le Goater wrote: > This requires a link to the chip to add the regions under the XSCOM > address space. This change will help us providing support for user > created PHB3 devices. > > Signed-off-by: Cédric Le Goater <clg@kaod.org> > --- Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> > include/hw/pci-host/pnv_phb3.h | 3 +++ > hw/pci-host/pnv_phb3.c | 1 + > hw/pci-host/pnv_phb3_pbcq.c | 11 +++++++++++ > hw/ppc/pnv.c | 14 ++------------ > 4 files changed, 17 insertions(+), 12 deletions(-) > > diff --git a/include/hw/pci-host/pnv_phb3.h b/include/hw/pci-host/pnv_phb3.h > index e2a2e3624532..e9c13e6bd821 100644 > --- a/include/hw/pci-host/pnv_phb3.h > +++ b/include/hw/pci-host/pnv_phb3.h > @@ -16,6 +16,7 @@ > #include "qom/object.h" > > typedef struct PnvPHB3 PnvPHB3; > +typedef struct PnvChip PnvChip; > > /* > * PHB3 XICS Source for MSIs > @@ -157,6 +158,8 @@ struct PnvPHB3 { > PnvPHB3RootPort root; > > QLIST_HEAD(, PnvPhb3DMASpace) dma_spaces; > + > + PnvChip *chip; > }; > > uint64_t pnv_phb3_reg_read(void *opaque, hwaddr off, unsigned size); > diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c > index a7f96850055a..3aa42ef9d4b9 100644 > --- a/hw/pci-host/pnv_phb3.c > +++ b/hw/pci-host/pnv_phb3.c > @@ -1092,6 +1092,7 @@ static const char *pnv_phb3_root_bus_path(PCIHostState *host_bridge, > static Property pnv_phb3_properties[] = { > DEFINE_PROP_UINT32("index", PnvPHB3, phb_id, 0), > DEFINE_PROP_UINT32("chip-id", PnvPHB3, chip_id, 0), > + DEFINE_PROP_LINK("chip", PnvPHB3, chip, TYPE_PNV_CHIP, PnvChip *), > DEFINE_PROP_END_OF_LIST(), > }; > > diff --git a/hw/pci-host/pnv_phb3_pbcq.c b/hw/pci-host/pnv_phb3_pbcq.c > index a0526aa1eca3..c7426cd27a20 100644 > --- a/hw/pci-host/pnv_phb3_pbcq.c > +++ b/hw/pci-host/pnv_phb3_pbcq.c > @@ -284,6 +284,17 @@ static void pnv_pbcq_realize(DeviceState *dev, Error **errp) > pnv_xscom_region_init(&pbcq->xscom_spci_regs, OBJECT(dev), > &pnv_pbcq_spci_xscom_ops, pbcq, name, > PNV_XSCOM_PBCQ_SPCI_SIZE); > + > + /* Populate the XSCOM address space. */ > + pnv_xscom_add_subregion(phb->chip, > + PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id, > + &pbcq->xscom_nest_regs); > + pnv_xscom_add_subregion(phb->chip, > + PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id, > + &pbcq->xscom_pci_regs); > + pnv_xscom_add_subregion(phb->chip, > + PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id, > + &pbcq->xscom_spci_regs); > } > > static int pnv_pbcq_dt_xscom(PnvXScomInterface *dev, void *fdt, > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index 988b305398b2..de277c457838 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -1221,25 +1221,15 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) > /* PHB3 controllers */ > for (i = 0; i < chip->num_phbs; i++) { > PnvPHB3 *phb = &chip8->phbs[i]; > - PnvPBCQState *pbcq = &phb->pbcq; > > object_property_set_int(OBJECT(phb), "index", i, &error_fatal); > object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, > &error_fatal); > + object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), > + &error_fatal); > if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { > return; > } > - > - /* Populate the XSCOM address space. */ > - pnv_xscom_add_subregion(chip, > - PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id, > - &pbcq->xscom_nest_regs); > - pnv_xscom_add_subregion(chip, > - PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id, > - &pbcq->xscom_pci_regs); > - pnv_xscom_add_subregion(chip, > - PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id, > - &pbcq->xscom_spci_regs); > } > } > >
On 02/12/2021 15:42, Cédric Le Goater wrote: > This requires a link to the chip to add the regions under the XSCOM > address space. This change will help us providing support for user > created PHB3 devices. > > Signed-off-by: Cédric Le Goater <clg@kaod.org> > --- Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> > include/hw/pci-host/pnv_phb3.h | 3 +++ > hw/pci-host/pnv_phb3.c | 1 + > hw/pci-host/pnv_phb3_pbcq.c | 11 +++++++++++ > hw/ppc/pnv.c | 14 ++------------ > 4 files changed, 17 insertions(+), 12 deletions(-) > > diff --git a/include/hw/pci-host/pnv_phb3.h b/include/hw/pci-host/pnv_phb3.h > index e2a2e3624532..e9c13e6bd821 100644 > --- a/include/hw/pci-host/pnv_phb3.h > +++ b/include/hw/pci-host/pnv_phb3.h > @@ -16,6 +16,7 @@ > #include "qom/object.h" > > typedef struct PnvPHB3 PnvPHB3; > +typedef struct PnvChip PnvChip; > > /* > * PHB3 XICS Source for MSIs > @@ -157,6 +158,8 @@ struct PnvPHB3 { > PnvPHB3RootPort root; > > QLIST_HEAD(, PnvPhb3DMASpace) dma_spaces; > + > + PnvChip *chip; > }; > > uint64_t pnv_phb3_reg_read(void *opaque, hwaddr off, unsigned size); > diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c > index a7f96850055a..3aa42ef9d4b9 100644 > --- a/hw/pci-host/pnv_phb3.c > +++ b/hw/pci-host/pnv_phb3.c > @@ -1092,6 +1092,7 @@ static const char *pnv_phb3_root_bus_path(PCIHostState *host_bridge, > static Property pnv_phb3_properties[] = { > DEFINE_PROP_UINT32("index", PnvPHB3, phb_id, 0), > DEFINE_PROP_UINT32("chip-id", PnvPHB3, chip_id, 0), > + DEFINE_PROP_LINK("chip", PnvPHB3, chip, TYPE_PNV_CHIP, PnvChip *), > DEFINE_PROP_END_OF_LIST(), > }; > > diff --git a/hw/pci-host/pnv_phb3_pbcq.c b/hw/pci-host/pnv_phb3_pbcq.c > index a0526aa1eca3..c7426cd27a20 100644 > --- a/hw/pci-host/pnv_phb3_pbcq.c > +++ b/hw/pci-host/pnv_phb3_pbcq.c > @@ -284,6 +284,17 @@ static void pnv_pbcq_realize(DeviceState *dev, Error **errp) > pnv_xscom_region_init(&pbcq->xscom_spci_regs, OBJECT(dev), > &pnv_pbcq_spci_xscom_ops, pbcq, name, > PNV_XSCOM_PBCQ_SPCI_SIZE); > + > + /* Populate the XSCOM address space. */ > + pnv_xscom_add_subregion(phb->chip, > + PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id, > + &pbcq->xscom_nest_regs); > + pnv_xscom_add_subregion(phb->chip, > + PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id, > + &pbcq->xscom_pci_regs); > + pnv_xscom_add_subregion(phb->chip, > + PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id, > + &pbcq->xscom_spci_regs); > } > > static int pnv_pbcq_dt_xscom(PnvXScomInterface *dev, void *fdt, > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index 988b305398b2..de277c457838 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -1221,25 +1221,15 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) > /* PHB3 controllers */ > for (i = 0; i < chip->num_phbs; i++) { > PnvPHB3 *phb = &chip8->phbs[i]; > - PnvPBCQState *pbcq = &phb->pbcq; > > object_property_set_int(OBJECT(phb), "index", i, &error_fatal); > object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, > &error_fatal); > + object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), > + &error_fatal); > if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { > return; > } > - > - /* Populate the XSCOM address space. */ > - pnv_xscom_add_subregion(chip, > - PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id, > - &pbcq->xscom_nest_regs); > - pnv_xscom_add_subregion(chip, > - PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id, > - &pbcq->xscom_pci_regs); > - pnv_xscom_add_subregion(chip, > - PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id, > - &pbcq->xscom_spci_regs); > } > } > >
diff --git a/include/hw/pci-host/pnv_phb3.h b/include/hw/pci-host/pnv_phb3.h index e2a2e3624532..e9c13e6bd821 100644 --- a/include/hw/pci-host/pnv_phb3.h +++ b/include/hw/pci-host/pnv_phb3.h @@ -16,6 +16,7 @@ #include "qom/object.h" typedef struct PnvPHB3 PnvPHB3; +typedef struct PnvChip PnvChip; /* * PHB3 XICS Source for MSIs @@ -157,6 +158,8 @@ struct PnvPHB3 { PnvPHB3RootPort root; QLIST_HEAD(, PnvPhb3DMASpace) dma_spaces; + + PnvChip *chip; }; uint64_t pnv_phb3_reg_read(void *opaque, hwaddr off, unsigned size); diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c index a7f96850055a..3aa42ef9d4b9 100644 --- a/hw/pci-host/pnv_phb3.c +++ b/hw/pci-host/pnv_phb3.c @@ -1092,6 +1092,7 @@ static const char *pnv_phb3_root_bus_path(PCIHostState *host_bridge, static Property pnv_phb3_properties[] = { DEFINE_PROP_UINT32("index", PnvPHB3, phb_id, 0), DEFINE_PROP_UINT32("chip-id", PnvPHB3, chip_id, 0), + DEFINE_PROP_LINK("chip", PnvPHB3, chip, TYPE_PNV_CHIP, PnvChip *), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/pci-host/pnv_phb3_pbcq.c b/hw/pci-host/pnv_phb3_pbcq.c index a0526aa1eca3..c7426cd27a20 100644 --- a/hw/pci-host/pnv_phb3_pbcq.c +++ b/hw/pci-host/pnv_phb3_pbcq.c @@ -284,6 +284,17 @@ static void pnv_pbcq_realize(DeviceState *dev, Error **errp) pnv_xscom_region_init(&pbcq->xscom_spci_regs, OBJECT(dev), &pnv_pbcq_spci_xscom_ops, pbcq, name, PNV_XSCOM_PBCQ_SPCI_SIZE); + + /* Populate the XSCOM address space. */ + pnv_xscom_add_subregion(phb->chip, + PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id, + &pbcq->xscom_nest_regs); + pnv_xscom_add_subregion(phb->chip, + PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id, + &pbcq->xscom_pci_regs); + pnv_xscom_add_subregion(phb->chip, + PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id, + &pbcq->xscom_spci_regs); } static int pnv_pbcq_dt_xscom(PnvXScomInterface *dev, void *fdt, diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 988b305398b2..de277c457838 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1221,25 +1221,15 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) /* PHB3 controllers */ for (i = 0; i < chip->num_phbs; i++) { PnvPHB3 *phb = &chip8->phbs[i]; - PnvPBCQState *pbcq = &phb->pbcq; object_property_set_int(OBJECT(phb), "index", i, &error_fatal); object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, &error_fatal); + object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), + &error_fatal); if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { return; } - - /* Populate the XSCOM address space. */ - pnv_xscom_add_subregion(chip, - PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id, - &pbcq->xscom_nest_regs); - pnv_xscom_add_subregion(chip, - PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id, - &pbcq->xscom_pci_regs); - pnv_xscom_add_subregion(chip, - PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id, - &pbcq->xscom_spci_regs); } }
This requires a link to the chip to add the regions under the XSCOM address space. This change will help us providing support for user created PHB3 devices. Signed-off-by: Cédric Le Goater <clg@kaod.org> --- include/hw/pci-host/pnv_phb3.h | 3 +++ hw/pci-host/pnv_phb3.c | 1 + hw/pci-host/pnv_phb3_pbcq.c | 11 +++++++++++ hw/ppc/pnv.c | 14 ++------------ 4 files changed, 17 insertions(+), 12 deletions(-)