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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id f4sm2087955pfg.34.2021.12.09.23.58.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Dec 2021 23:58:49 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Subject: [PATCH v11 30/77] target/riscv: rvv-1.0: find-first-set mask bit instruction Date: Fri, 10 Dec 2021 15:56:16 +0800 Message-Id: <20211210075704.23951-31-frank.chang@sifive.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211210075704.23951-1-frank.chang@sifive.com> References: <20211210075704.23951-1-frank.chang@sifive.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::636 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Frank Chang , Bin Meng , Richard Henderson , Alistair Francis , Palmer Dabbelt , LIU Zhiwei Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/helper.h | 2 +- target/riscv/insn32.decode | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 4 ++-- target/riscv/vector_helper.c | 6 +++--- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 3f30882aec..7646567eb2 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1022,7 +1022,7 @@ DEF_HELPER_6(vmxnor_mm, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_4(vcpop_m, tl, ptr, ptr, env, i32) -DEF_HELPER_4(vmfirst_m, tl, ptr, ptr, env, i32) +DEF_HELPER_4(vfirst_m, tl, ptr, ptr, env, i32) DEF_HELPER_5(vmsbf_m, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vmsif_m, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index e748f7ca71..4df2aa9cdd 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -628,7 +628,7 @@ vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r vcpop_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm -vmfirst_m 010101 . ..... ----- 010 ..... 1010111 @r2_vm +vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm vmsof_m 010110 . ..... 00010 010 ..... 1010111 @r2_vm diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index b53cd2e6f3..3645bb9635 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2696,7 +2696,7 @@ static bool trans_vcpop_m(DisasContext *s, arg_rmr *a) } /* vmfirst find-first-set mask bit */ -static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a) +static bool trans_vfirst_m(DisasContext *s, arg_rmr *a) { if (require_rvv(s) && vext_check_isa_ill(s)) { @@ -2715,7 +2715,7 @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a) tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); - gen_helper_vmfirst_m(dst, mask, src2, cpu_env, desc); + gen_helper_vfirst_m(dst, mask, src2, cpu_env, desc); gen_set_gpr(s, a->rd, dst); tcg_temp_free_ptr(mask); diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 9451112b3d..f97783acf0 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4233,9 +4233,9 @@ target_ulong HELPER(vcpop_m)(void *v0, void *vs2, CPURISCVState *env, return cnt; } -/* vmfirst find-first-set mask bit*/ -target_ulong HELPER(vmfirst_m)(void *v0, void *vs2, CPURISCVState *env, - uint32_t desc) +/* vfirst find-first-set mask bit*/ +target_ulong HELPER(vfirst_m)(void *v0, void *vs2, CPURISCVState *env, + uint32_t desc) { uint32_t vm = vext_vm(desc); uint32_t vl = env->vl;