[v11,42/77] target/riscv: rvv-1.0: single-width bit shift instructions

From: Frank Chang <frank.chang@sifive.com>

From: frank.chang@sifive.com
To: qemu-devel@nongnu.org
Subject: [PATCH v11 42/77] target/riscv: rvv-1.0: single-width bit shift
 instructions
Date: Fri, 10 Dec 2021 15:56:28 +0800
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Cc: qemu-riscv@nongnu.org, Frank Chang <frank.chang@sifive.com>,
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Message ID	20211210075704.23951-43-frank.chang@sifive.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org> From: frank.chang@sifive.com To: qemu-devel@nongnu.org Subject: [PATCH v11 42/77] target/riscv: rvv-1.0: single-width bit shift instructions Date: Fri, 10 Dec 2021 15:56:28 +0800 Message-Id: <20211210075704.23951-43-frank.chang@sifive.com> In-Reply-To: <20211210075704.23951-1-frank.chang@sifive.com> References: <20211210075704.23951-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=frank.chang@sifive.com; helo=mail-pg1-x529.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action Precedence: list Cc: qemu-riscv@nongnu.org, Frank Chang <frank.chang@sifive.com>, Bin Meng <bin.meng@windriver.com>, Richard Henderson <richard.henderson@linaro.org>, Alistair Francis <alistair.francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, LIU Zhiwei <zhiwei_liu@c-sky.com> Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org>
Series	support vector extension v1.0 \| expand [v11,00/77] support vector extension v1.0 [v11,01/77] target/riscv: drop vector 0.7.1 and add 1.0 support [v11,02/77] target/riscv: Use FIELD_EX32() to extract wd field [v11,03/77] target/riscv: rvv-1.0: add mstatus VS field [v11,04/77] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty [v11,05/77] target/riscv: rvv-1.0: add sstatus VS field [v11,06/77] target/riscv: rvv-1.0: introduce writable misa.v field [v11,07/77] target/riscv: rvv-1.0: add translation-time vector context status [v11,08/77] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers [v11,09/77] target/riscv: rvv-1.0: add vcsr register [v11,10/77] target/riscv: rvv-1.0: add vlenb register [v11,11/77] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers [v11,12/77] target/riscv: rvv-1.0: remove MLEN calculations [v11,13/77] target/riscv: rvv-1.0: add fractional LMUL [v11,14/77] target/riscv: rvv-1.0: add VMA and VTA [v11,15/77] target/riscv: rvv-1.0: update check functions [v11,16/77] target/riscv: introduce more imm value modes in translator functions [v11,17/77] target/riscv: rvv:1.0: add translation-time nan-box helper function [v11,18/77] target/riscv: rvv-1.0: remove amo operations instructions [v11,19/77] target/riscv: rvv-1.0: configure instructions [v11,20/77] target/riscv: rvv-1.0: stride load and store instructions [v11,21/77] target/riscv: rvv-1.0: index load and store instructions [v11,22/77] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns [v11,23/77] target/riscv: rvv-1.0: fault-only-first unit stride load [v11,24/77] target/riscv: rvv-1.0: load/store whole register instructions [v11,25/77] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns [v11,26/77] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation [v11,27/77] target/riscv: rvv-1.0: floating-point square-root instruction [v11,28/77] target/riscv: rvv-1.0: floating-point classify instructions [v11,29/77] target/riscv: rvv-1.0: count population in mask instruction [v11,30/77] target/riscv: rvv-1.0: find-first-set mask bit instruction [v11,31/77] target/riscv: rvv-1.0: set-X-first mask bit instructions [v11,32/77] target/riscv: rvv-1.0: iota instruction [v11,33/77] target/riscv: rvv-1.0: element index instruction [v11,34/77] target/riscv: rvv-1.0: allow load element with sign-extended [v11,35/77] target/riscv: rvv-1.0: register gather instructions [v11,36/77] target/riscv: rvv-1.0: integer scalar move instructions [v11,37/77] target/riscv: rvv-1.0: floating-point move instruction [v11,38/77] target/riscv: rvv-1.0: floating-point scalar move instructions [v11,39/77] target/riscv: rvv-1.0: whole register move instructions [v11,40/77] target/riscv: rvv-1.0: integer extension instructions [v11,41/77] target/riscv: rvv-1.0: single-width averaging add and subtract instructions [v11,42/77] target/riscv: rvv-1.0: single-width bit shift instructions [v11,43/77] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow [v11,44/77] target/riscv: rvv-1.0: narrowing integer right shift instructions [v11,45/77] target/riscv: rvv-1.0: widening integer multiply-add instructions [v11,46/77] target/riscv: rvv-1.0: single-width saturating add and subtract instructions [v11,47/77] target/riscv: rvv-1.0: integer comparison instructions [v11,48/77] target/riscv: rvv-1.0: floating-point compare instructions [v11,49/77] target/riscv: rvv-1.0: mask-register logical instructions [v11,50/77] target/riscv: rvv-1.0: slide instructions [v11,51/77] target/riscv: rvv-1.0: floating-point slide instructions [v11,52/77] target/riscv: rvv-1.0: narrowing fixed-point clip instructions [v11,53/77] target/riscv: rvv-1.0: single-width floating-point reduction [v11,54/77] target/riscv: rvv-1.0: widening floating-point reduction instructions [v11,55/77] target/riscv: rvv-1.0: single-width scaling shift instructions [v11,56/77] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add [v11,57/77] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf [v11,58/77] target/riscv: rvv-1.0: remove integer extract instruction [v11,59/77] target/riscv: rvv-1.0: floating-point min/max instructions [v11,60/77] target/riscv: introduce floating-point rounding mode enum [v11,61/77] target/riscv: rvv-1.0: floating-point/integer type-convert instructions [v11,62/77] target/riscv: rvv-1.0: widening floating-point/integer type-convert [v11,63/77] target/riscv: add "set round to odd" rounding mode helper function [v11,64/77] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert [v11,65/77] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits [v11,66/77] target/riscv: rvv-1.0: implement vstart CSR [v11,67/77] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid [v11,68/77] target/riscv: gdb: support vector registers for rv64 & rv32 [v11,69/77] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction [v11,70/77] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction [v11,71/77] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 [v11,72/77] target/riscv: rvv-1.0: add vsetivli instruction [v11,73/77] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() [v11,74/77] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns [v11,75/77] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm [v11,76/77] target/riscv: rvv-1.0: update opivv_vadc_check() comment [v11,77/77] target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions

[v11,42/77] target/riscv: rvv-1.0: single-width bit shift instructions

Commit Message

Patch