From patchwork Fri Dec 10 07:56:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Chang X-Patchwork-Id: 12669061 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 840C4C433EF for ; Fri, 10 Dec 2021 09:15:25 +0000 (UTC) Received: from localhost ([::1]:60538 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mvbzw-0003Zu-I4 for qemu-devel@archiver.kernel.org; Fri, 10 Dec 2021 04:15:24 -0500 Received: from eggs.gnu.org ([209.51.188.92]:34662) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mvapp-0000lh-7v for qemu-devel@nongnu.org; Fri, 10 Dec 2021 03:00:53 -0500 Received: from [2607:f8b0:4864:20::102a] (port=43756 helo=mail-pj1-x102a.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1mvaph-0008CH-1g for qemu-devel@nongnu.org; Fri, 10 Dec 2021 03:00:52 -0500 Received: by mail-pj1-x102a.google.com with SMTP id nh10-20020a17090b364a00b001a69adad5ebso6872175pjb.2 for ; Fri, 10 Dec 2021 00:00:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tlfo0cSvfe+EcMV73lW1RdpdLIcQKGUGA5CQlKVfIxs=; b=YsWiSa2C0rMgzLKIyzIjVJz9426aLe0ifEuO9hKgz3LjTEz+FGZRE1xKraea3W1EN4 OJW6EhAZkWrn+rqVV3u+1F7M+ofK6OzZTbM0aulIn/107Z/8nlG8zOkIGuA4rUql7nKW 9Cc0bUtzS4pcPjE91CkIeCikOpXJbuBweWArXVdF+i5NerwqyUCAv9mWk9wNrYIBB9QX bBTOZVbCNCoApySuBLxeAHlJJ8/olpLIwOO9apLhiwNSuTze5WYVRvCVDOgXkOxTDOW6 fX6RHatRNiKpm8yRSovySXgS6PcPsk5lqIQpNXpFv7AN7zjmBvaCdGubCGUyP5xq8lHV tE8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tlfo0cSvfe+EcMV73lW1RdpdLIcQKGUGA5CQlKVfIxs=; b=npm+auut/mcCneeRFbG998nTBhiRWT8zSTEg+fSXnD+HgzReYVzYg2+jBXh2ZNp1N0 3sc+DQI8Y3YbG0PqrUzB4DxeSDzYuxByIVIDUXzqJT6gE6SRAsDSiEJkcqbBLoAcez5y LBjLYa0y2+V0PneJNQQ+jMzCnRT3XYmn702LNdN0zEs25eFhb10m9xEmg5vxqQyGMkjd JCIdJ/VRKJmkQA2tTlue7cCrdk+ydETXhJDoIapDGxtfip/fppTr/j9vYYksvhu8YLUX XSNmlYlEYbxJGEqBlPFQb/AL+wUo+QVNqlQPu9hif09DBmVW5HRTH+CoNlfbLTh91g5g oOVA== X-Gm-Message-State: AOAM530X6yvtCtnCIMF3tLhEwUrIXyX1YVeRg2BIZQxcg9KklH+QK+QM vDo1BtjfTJdn+liHqk8xPajRVrlhaAZ+jABb X-Google-Smtp-Source: ABdhPJzjmfzrcgM9ZsVnnEy5stHw1im8drLDMHkEMxMLuRa4ilxp8ny5UnnIHpNnSsukaq3i6WOqtA== X-Received: by 2002:a17:902:f687:b0:141:cf6b:fee7 with SMTP id l7-20020a170902f68700b00141cf6bfee7mr72055123plg.75.1639123243123; Fri, 10 Dec 2021 00:00:43 -0800 (PST) Received: from hsinchu16.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id f4sm2087955pfg.34.2021.12.10.00.00.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Dec 2021 00:00:42 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Subject: [PATCH v11 73/77] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() Date: Fri, 10 Dec 2021 15:56:59 +0800 Message-Id: <20211210075704.23951-74-frank.chang@sifive.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20211210075704.23951-1-frank.chang@sifive.com> References: <20211210075704.23951-1-frank.chang@sifive.com> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102a (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x102a.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Bin Meng , qemu-riscv@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang Add supports of Vector unit-stride mask load/store instructions (vlm.v, vsm.v), which has: evl (effective vector length) = ceil(env->vl / 8). The new instructions operate the same as unmasked byte loads and stores. Add evl parameter to reuse vext_ldst_us(). Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/vector_helper.c | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 946dca53ff..83373ca6fc 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -279,15 +279,15 @@ GEN_VEXT_ST_STRIDE(vsse64_v, int64_t, ste_d) /* unmasked unit-stride load and store operation*/ static void vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc, - vext_ldst_elem_fn *ldst_elem, - uint32_t esz, uintptr_t ra, MMUAccessType access_type) + vext_ldst_elem_fn *ldst_elem, uint32_t esz, uint32_t evl, + uintptr_t ra, MMUAccessType access_type) { uint32_t i, k; uint32_t nf = vext_nf(desc); uint32_t max_elems = vext_max_elems(desc, esz); /* load bytes from guest memory */ - for (i = env->vstart; i < env->vl; i++, env->vstart++) { + for (i = env->vstart; i < evl; i++, env->vstart++) { k = 0; while (k < nf) { target_ulong addr = base + ((i * nf + k) << esz); @@ -316,7 +316,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ CPURISCVState *env, uint32_t desc) \ { \ vext_ldst_us(vd, base, env, desc, LOAD_FN, \ - ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_LOAD); \ + ctzl(sizeof(ETYPE)), env->vl, GETPC(), MMU_DATA_LOAD); \ } GEN_VEXT_LD_US(vle8_v, int8_t, lde_b) @@ -324,20 +324,20 @@ GEN_VEXT_LD_US(vle16_v, int16_t, lde_h) GEN_VEXT_LD_US(vle32_v, int32_t, lde_w) GEN_VEXT_LD_US(vle64_v, int64_t, lde_d) -#define GEN_VEXT_ST_US(NAME, ETYPE, STORE_FN) \ -void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \ - CPURISCVState *env, uint32_t desc) \ -{ \ - uint32_t stride = vext_nf(desc) << ctzl(sizeof(ETYPE)); \ - vext_ldst_stride(vd, v0, base, stride, env, desc, false, STORE_FN, \ - ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_STORE); \ -} \ - \ -void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ - CPURISCVState *env, uint32_t desc) \ -{ \ - vext_ldst_us(vd, base, env, desc, STORE_FN, \ - ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_STORE); \ +#define GEN_VEXT_ST_US(NAME, ETYPE, STORE_FN) \ +void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t stride = vext_nf(desc) << ctzl(sizeof(ETYPE)); \ + vext_ldst_stride(vd, v0, base, stride, env, desc, false, STORE_FN, \ + ctzl(sizeof(ETYPE)), GETPC(), MMU_DATA_STORE); \ +} \ + \ +void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + vext_ldst_us(vd, base, env, desc, STORE_FN, \ + ctzl(sizeof(ETYPE)), env->vl, GETPC(), MMU_DATA_STORE); \ } GEN_VEXT_ST_US(vse8_v, int8_t, ste_b)