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Sat, 11 Dec 2021 04:19:58 +0000 From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Subject: [PATCH v5 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode Date: Sat, 11 Dec 2021 09:48:55 +0530 Message-Id: <20211211041917.135345-2-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211211041917.135345-1-anup.patel@wdc.com> References: <20211211041917.135345-1-anup.patel@wdc.com> X-ClientProxiedBy: MA1PR0101CA0041.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:22::27) To CO6PR04MB7812.namprd04.prod.outlook.com (2603:10b6:303:138::6) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b11c1caa-065c-4ef9-0327-08d9bc5d7d92 X-MS-TrafficTypeDiagnostic: CO1PR04MB8265:EE_ X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:519; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: w1jfQ07z3e5Bjk1Un05lYYo0ceWTZZfLixyR70BT/5jbffcaAO2AO9x6u7FfT6VqAIneJjpL8Tx4aVyNUtJiarLZYG4HqE6vKDlqCCAVclRXrEcPoVGxdMsOjbiLhQiq1MrOJOa6y0FjDakDe5x/oEmHrJloX7NHLnXiX5y1aDiUOTPlD18enjbB+FVSobQKSGmC95MYeZNTniKnubZsdv76uFUpxoix5AzXklhOIMwmsUKlqFzPklAXuqPyqNFD9NpVnx+ipbRWNRGUWLgb/40D1aBCSx2tuVKGpCcnymZ2XgBGKjNfd3Y6wdbSssQszDUXxym4I7XY3t0j5AV0OeolLzTkbtuEN0kJ8AXQakgisHaAEiu30DluUxUXmMiNBjoyi8dhxnnWW/iLRPbl7o11mbGQO2dnvyx9fzTGN5gmD+FYfidRWNMVr3cq/7L2UVY6BGPlOLiOS20m3+J+6pmubmVBQsM9RWiwRkaVLvigkBT4r0S8RFrBgkZ/Xzf88gEddej/7bAJNHu7C3UBZCGh9gaqK3ZOgDAbthzz7xnM+BjdKtuOXOwN05xqTcjUwHnYMcZjk6ur6ZY5SYDczCJOaI7cAILTkwcNcYkGXqL2zCcCbQNiO3C6OuCOhqjvt2ZT1VR0d6lVZZQWwHqzCXXKvdnn8xcUS+VDUzcpOKgstojxM0gzmvO66T9qDYbd1IzGOj+Lq+tW6+8JmDf8BA== X-Forefront-Antispam-Report: CIP:255.255.255.255; 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envelope-from=prvs=972e533d7=Anup.Patel@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Anup Patel , Anup Patel , qemu-devel@nongnu.org, Alistair Francis , Atish Patra , Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" We should be returning illegal instruction trap when RV64 HS-mode tries to access RV32 HS-mode CSR. Fixes: d6f20dacea51 ("target/riscv: Fix 32-bit HS mode access permissions") Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 9f41954894..d170c7fd08 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -181,7 +181,7 @@ static RISCVException hmode(CPURISCVState *env, int csrno) static RISCVException hmode32(CPURISCVState *env, int csrno) { if (riscv_cpu_mxl(env) != MXL_RV32) { - if (riscv_cpu_virt_enabled(env)) { + if (!riscv_cpu_virt_enabled(env)) { return RISCV_EXCP_ILLEGAL_INST; } else { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;