Message ID | 20211211041917.135345-24-anup.patel@wdc.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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Sat, 11 Dec 2021 04:21:10 +0000 From: Anup Patel <anup.patel@wdc.com> To: Peter Maydell <peter.maydell@linaro.org>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, Sagar Karandikar <sagark@eecs.berkeley.edu> Subject: [PATCH v5 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs Date: Sat, 11 Dec 2021 09:49:17 +0530 Message-Id: <20211211041917.135345-24-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211211041917.135345-1-anup.patel@wdc.com> References: <20211211041917.135345-1-anup.patel@wdc.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: MA1PR0101CA0041.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:22::27) To CO6PR04MB7812.namprd04.prod.outlook.com (2603:10b6:303:138::6) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b7b6fb0e-3852-4cda-18f5-08d9bc5da898 X-MS-TrafficTypeDiagnostic: CO1PR04MB8268:EE_ X-Microsoft-Antispam-PRVS: <CO1PR04MB826882C3AC1A3FD77CFF258B8D729@CO1PR04MB8268.namprd04.prod.outlook.com> WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:5516; 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QEMU RISC-V AIA support
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expand
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diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 74e9e333d1..68ab915525 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -44,6 +44,16 @@ #include "hw/pci-host/gpex.h" #include "hw/display/ramfb.h" +/* + * The virt machine physical address space used by some of the devices + * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets, + * number of CPUs, and number of IMSIC guest files. + * + * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS, + * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization + * of virt machine physical address space. + */ + #define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT) #if VIRT_IMSIC_GROUP_MAX_SIZE < \ IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS) diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index e12e8ddcae..62d8e9c6d0 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -24,7 +24,7 @@ #include "hw/block/flash.h" #include "qom/object.h" -#define VIRT_CPUS_MAX_BITS 3 +#define VIRT_CPUS_MAX_BITS 9 #define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS) #define VIRT_SOCKETS_MAX_BITS 2 #define VIRT_SOCKETS_MAX (1 << VIRT_SOCKETS_MAX_BITS)
To facilitate software development of RISC-V systems with large number of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9). We also add a detailed source level comments about limit defines which impact the physical address space utilization. Signed-off-by: Anup Patel <anup.patel@wdc.com> --- hw/riscv/virt.c | 10 ++++++++++ include/hw/riscv/virt.h | 2 +- 2 files changed, 11 insertions(+), 1 deletion(-)