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Sat, 11 Dec 2021 04:20:01 +0000 From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Subject: [PATCH v5 02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs Date: Sat, 11 Dec 2021 09:48:56 +0530 Message-Id: <20211211041917.135345-3-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211211041917.135345-1-anup.patel@wdc.com> References: <20211211041917.135345-1-anup.patel@wdc.com> X-ClientProxiedBy: MA1PR0101CA0041.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:22::27) To CO6PR04MB7812.namprd04.prod.outlook.com (2603:10b6:303:138::6) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 518365fb-a9ac-40a1-fc0f-08d9bc5d7fc4 X-MS-TrafficTypeDiagnostic: CO1PR04MB8265:EE_ X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:229; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 8rCUnNfddB12lZdKeDz5V5zwX5qmjfgXp/umqWNOC4QDJC0icHWsn0dQcnoojhbQmRsK2etiAEp7mm55wmRmAjn2278bJCcph24KPT8miHhpVokBhewWlmwn+ut8grUAlOziva4+O9oDr4N/3al4hjA2Yoyg85S8NQzE8TBULVtw2KUX4LaQfAyUAXPg4ydjK2dB+B/ASH822+xtRAaVV98+3fwRYSOsWQjrGfDlynzcuqUuL4Ame/gNR51XMivxFjcRgJ7PxDaGyBhfoq9ljBHr2CK+quyT8/Etd868nAWZLeMLlK6DjDePQWzLudtAVe+L2zBe1bRVvsra/WyaX4UnkBt/BNj1kiFpV0XewBrTwNeJYNvWkZrmzTaLyJGzppmNMGJBG4fWlKUK04sxM+R01XXoZKnDnDMUQzNyLVYy1UrL5g2nbkNzzJvuYIQk+UrLcm33bnpVYYx4ZSV4qTJ7brIi8YjiGp2nTUxrKQ9Llwy1ndp6oMRwgLpfTa/riwwdr1JRVy7J5AAJH28eREK2ih7FsCOQ7j+Fl+XAX4IjnEOAYjN99n/MsbnI6BBUnpYrJBXGfk+QCqtt25eQU7BTO9tyuPiRaJwsbGCuRHJ+FX5MIUIdTs1fRyUKySy90m7HB39rsBDv3GtFdemfHdgK9xPAm9YU6XIaY3Jcn6ZDlQBLcSEhdDRqHWse/MT+o/F1QcdNizI4yIV22lUu1Q== X-Forefront-Antispam-Report: CIP:255.255.255.255; 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envelope-from=prvs=972e533d7=Anup.Patel@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Anup Patel , Anup Patel , qemu-devel@nongnu.org, Alistair Francis , Atish Patra , Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" A hypervisor can optionally take guest external interrupts using SGEIP bit of hip and hie CSRs. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 3 ++- target/riscv/cpu_bits.h | 3 +++ target/riscv/csr.c | 18 +++++++++++------- 3 files changed, 16 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f812998123..f3b1b9a775 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -372,6 +372,7 @@ static void riscv_cpu_reset(DeviceState *dev) env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); } env->mcause = 0; + env->miclaim = MIP_SGEIP; env->pc = env->resetvec; env->two_stage_lookup = false; /* mmte is supposed to have pm.current hardwired to 1 */ @@ -610,7 +611,7 @@ static void riscv_cpu_init(Object *obj) cpu_set_cpustate_pointers(cpu); #ifndef CONFIG_USER_ONLY - qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12); + qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX); #endif /* CONFIG_USER_ONLY */ } diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 9913fa9f77..c8ce77b1bb 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -524,6 +524,8 @@ typedef enum RISCVException { #define IRQ_S_EXT 9 #define IRQ_VS_EXT 10 #define IRQ_M_EXT 11 +#define IRQ_S_GEXT 12 +#define IRQ_LOCAL_MAX 16 /* mip masks */ #define MIP_USIP (1 << IRQ_U_SOFT) @@ -538,6 +540,7 @@ typedef enum RISCVException { #define MIP_SEIP (1 << IRQ_S_EXT) #define MIP_VSEIP (1 << IRQ_VS_EXT) #define MIP_MEIP (1 << IRQ_M_EXT) +#define MIP_SGEIP (1 << IRQ_S_GEXT) /* sip masks */ #define SIP_SSIP MIP_SSIP diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d170c7fd08..56e8d35217 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -418,12 +418,13 @@ static RISCVException read_timeh(CPURISCVState *env, int csrno, #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) +#define HS_MODE_INTERRUPTS (MIP_SGEIP | VS_MODE_INTERRUPTS) static const target_ulong delegable_ints = S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS; static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS; static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | - VS_MODE_INTERRUPTS; + HS_MODE_INTERRUPTS; #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \ (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \ @@ -683,7 +684,7 @@ static RISCVException write_mideleg(CPURISCVState *env, int csrno, { env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints); if (riscv_has_ext(env, RVH)) { - env->mideleg |= VS_MODE_INTERRUPTS; + env->mideleg |= HS_MODE_INTERRUPTS; } return RISCV_EXCP_NONE; } @@ -699,6 +700,9 @@ static RISCVException write_mie(CPURISCVState *env, int csrno, target_ulong val) { env->mie = (env->mie & ~all_ints) | (val & all_ints); + if (!riscv_has_ext(env, RVH)) { + env->mie &= ~MIP_SGEIP; + } return RISCV_EXCP_NONE; } @@ -994,7 +998,7 @@ static RISCVException rmw_sip(CPURISCVState *env, int csrno, } if (ret_value) { - *ret_value &= env->mideleg; + *ret_value &= env->mideleg & S_MODE_INTERRUPTS; } return ret; } @@ -1112,7 +1116,7 @@ static RISCVException rmw_hvip(CPURISCVState *env, int csrno, write_mask & hvip_writable_mask); if (ret_value) { - *ret_value &= hvip_writable_mask; + *ret_value &= VS_MODE_INTERRUPTS; } return ret; } @@ -1125,7 +1129,7 @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno, write_mask & hip_writable_mask); if (ret_value) { - *ret_value &= hip_writable_mask; + *ret_value &= HS_MODE_INTERRUPTS; } return ret; } @@ -1133,14 +1137,14 @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno, static RISCVException read_hie(CPURISCVState *env, int csrno, target_ulong *val) { - *val = env->mie & VS_MODE_INTERRUPTS; + *val = env->mie & HS_MODE_INTERRUPTS; return RISCV_EXCP_NONE; } static RISCVException write_hie(CPURISCVState *env, int csrno, target_ulong val) { - target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS); + target_ulong newval = (env->mie & ~HS_MODE_INTERRUPTS) | (val & HS_MODE_INTERRUPTS); return write_mie(env, CSR_MIE, newval); }