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Sat, 11 Dec 2021 04:20:11 +0000 From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Subject: [PATCH v5 05/23] target/riscv: Allow setting CPU feature from machine/device emulation Date: Sat, 11 Dec 2021 09:48:59 +0530 Message-Id: <20211211041917.135345-6-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211211041917.135345-1-anup.patel@wdc.com> References: <20211211041917.135345-1-anup.patel@wdc.com> X-ClientProxiedBy: MA1PR0101CA0041.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:22::27) To CO6PR04MB7812.namprd04.prod.outlook.com (2603:10b6:303:138::6) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 06f85a11-f0e7-4e2b-2892-08d9bc5d85cb X-MS-TrafficTypeDiagnostic: CO1PR04MB8265:EE_ X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:6430; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: xZYW6P7A4veTmsxFeeBslkqDEorLH2iJBwIUMiPbL3T5QvFAPsFTzO6jLYTLTO+qn1uQH54vQgxPFsVbXC+k0ez6Rl5H7EeU4C54nIZ9A8iPqJL/xTJjZEoNJ7hrS+IKeFVF1UnNsAsm6K6bJypSIM9aTTjFgw9XTySY5FzD7w+738ulLvLQJ9+rkNKUcCNkfvC2szbiIiA86nvQ6quLDgmsJgGSAPd7GsY8GESlYoK/Qi9sZmN6z+amE2D4Wi8EKKQqyZy85QfALy6xAPr3DhqUe/BQ/b5RPGqFex35qAAQABz+PyR6dJMH0AMUDFgYOGjSOu5Yx5iIecH/racTyodKRFD2+A/CqJM8Eh76HvCIH8mm2OUXp3N2TclqplJINPG31SB9jHmNn6uOvgKStvRkxA6r4q+FCP1Cmhhi/knJW1oOjEv0lHitYYb3/Xpdl1g865y3akjFQgX9v3nKBp9V/HLzGbK2D6xMGdCQIs+KWBKTiPyA2zbkOxS3/5BiOqfL4F699He1y511P7dZgX8WfjdmNOqcieKsFBF8+NvCoxLtLKpZBPfKJRGPTjSnVOIAEq04w+ms6lidviNFm5PDV3fGVH7L/qf+IXwhTzqIhXUy/Vg5zXYYBvPFKoMuubmsGhUHeu7FIol3FiW+NJkT6dbtoxKmOGWo9y0XZzPNn+CPlkzbdXzH0PIUZ0b9akXcB86E0Fajx9tzOdqsbA== X-Forefront-Antispam-Report: CIP:255.255.255.255; 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envelope-from=prvs=972e533d7=Anup.Patel@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Anup Patel , Anup Patel , qemu-devel@nongnu.org, Alistair Francis , Atish Patra , Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The machine or device emulation should be able to force set certain CPU features because: 1) We can have certain CPU features which are in-general optional but implemented by RISC-V CPUs on the machine. 2) We can have devices which require a certain CPU feature. For example, AIA IMSIC devices expect AIA CSRs implemented by RISC-V CPUs. Signed-off-by: Anup Patel Reviewed-by: Bin Meng Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 11 +++-------- target/riscv/cpu.h | 5 +++++ 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index da58a9654f..827cff0d2b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -124,11 +124,6 @@ static void set_vext_version(CPURISCVState *env, int vext_ver) env->vext_ver = vext_ver; } -static void set_feature(CPURISCVState *env, int feature) -{ - env->features |= (1ULL << feature); -} - static void set_resetvec(CPURISCVState *env, target_ulong resetvec) { #ifndef CONFIG_USER_ONLY @@ -434,18 +429,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } if (cpu->cfg.mmu) { - set_feature(env, RISCV_FEATURE_MMU); + riscv_set_feature(env, RISCV_FEATURE_MMU); } if (cpu->cfg.pmp) { - set_feature(env, RISCV_FEATURE_PMP); + riscv_set_feature(env, RISCV_FEATURE_PMP); /* * Enhanced PMP should only be available * on harts with PMP support */ if (cpu->cfg.epmp) { - set_feature(env, RISCV_FEATURE_EPMP); + riscv_set_feature(env, RISCV_FEATURE_EPMP); } } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 92a276f109..48637342ed 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -339,6 +339,11 @@ static inline bool riscv_feature(CPURISCVState *env, int feature) return env->features & (1ULL << feature); } +static inline void riscv_set_feature(CPURISCVState *env, int feature) +{ + env->features |= (1ULL << feature); +} + #include "cpu_user.h" extern const char * const riscv_int_regnames[];