| Message ID | 20211211041917.135345-8-anup.patel@wdc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | QEMU RISC-V AIA support | expand |
On Sat, Dec 11, 2021 at 2:22 PM Anup Patel <anup.patel@wdc.com> wrote: > > The RISC-V AIA specification extends RISC-V local interrupts and > introduces new CSRs. This patch adds defines for the new AIA CSRs. > > Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu_bits.h | 127 ++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 127 insertions(+) > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index 0c6ef6e51c..5b28e73506 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -160,6 +160,31 @@ > #define CSR_MTVAL 0x343 > #define CSR_MIP 0x344 > > +/* Machine-Level Window to Indirectly Accessed Registers (AIA) */ > +#define CSR_MISELECT 0x350 > +#define CSR_MIREG 0x351 > + > +/* Machine-Level Interrupts (AIA) */ > +#define CSR_MTOPI 0xfb0 > + > +/* Machine-Level IMSIC Interface (AIA) */ > +#define CSR_MSETEIPNUM 0x358 > +#define CSR_MCLREIPNUM 0x359 > +#define CSR_MSETEIENUM 0x35a > +#define CSR_MCLREIENUM 0x35b > +#define CSR_MTOPEI 0x35c > + > +/* Virtual Interrupts for Supervisor Level (AIA) */ > +#define CSR_MVIEN 0x308 > +#define CSR_MVIP 0x309 > + > +/* Machine-Level High-Half CSRs (AIA) */ > +#define CSR_MIDELEGH 0x313 > +#define CSR_MIEH 0x314 > +#define CSR_MVIENH 0x318 > +#define CSR_MVIPH 0x319 > +#define CSR_MIPH 0x354 > + > /* Supervisor Trap Setup */ > #define CSR_SSTATUS 0x100 > #define CSR_SEDELEG 0x102 > @@ -179,6 +204,24 @@ > #define CSR_SPTBR 0x180 > #define CSR_SATP 0x180 > > +/* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ > +#define CSR_SISELECT 0x150 > +#define CSR_SIREG 0x151 > + > +/* Supervisor-Level Interrupts (AIA) */ > +#define CSR_STOPI 0xdb0 > + > +/* Supervisor-Level IMSIC Interface (AIA) */ > +#define CSR_SSETEIPNUM 0x158 > +#define CSR_SCLREIPNUM 0x159 > +#define CSR_SSETEIENUM 0x15a > +#define CSR_SCLREIENUM 0x15b > +#define CSR_STOPEI 0x15c > + > +/* Supervisor-Level High-Half CSRs (AIA) */ > +#define CSR_SIEH 0x114 > +#define CSR_SIPH 0x154 > + > /* Hpervisor CSRs */ > #define CSR_HSTATUS 0x600 > #define CSR_HEDELEG 0x602 > @@ -209,6 +252,35 @@ > #define CSR_MTINST 0x34a > #define CSR_MTVAL2 0x34b > > +/* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ > +#define CSR_HVIEN 0x608 > +#define CSR_HVICTL 0x609 > +#define CSR_HVIPRIO1 0x646 > +#define CSR_HVIPRIO2 0x647 > + > +/* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */ > +#define CSR_VSISELECT 0x250 > +#define CSR_VSIREG 0x251 > + > +/* VS-Level Interrupts (H-extension with AIA) */ > +#define CSR_VSTOPI 0xeb0 > + > +/* VS-Level IMSIC Interface (H-extension with AIA) */ > +#define CSR_VSSETEIPNUM 0x258 > +#define CSR_VSCLREIPNUM 0x259 > +#define CSR_VSSETEIENUM 0x25a > +#define CSR_VSCLREIENUM 0x25b > +#define CSR_VSTOPEI 0x25c > + > +/* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ > +#define CSR_HIDELEGH 0x613 > +#define CSR_HVIENH 0x618 > +#define CSR_HVIPH 0x655 > +#define CSR_HVIPRIO1H 0x656 > +#define CSR_HVIPRIO2H 0x657 > +#define CSR_VSIEH 0x214 > +#define CSR_VSIPH 0x254 > + > /* Enhanced Physical Memory Protection (ePMP) */ > #define CSR_MSECCFG 0x747 > #define CSR_MSECCFGH 0x757 > @@ -619,4 +691,59 @@ typedef enum RISCVException { > #define UMTE_U_PM_INSN U_PM_INSN > #define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_INSN) > > +/* MISELECT, SISELECT, and VSISELECT bits (AIA) */ > +#define ISELECT_IPRIO0 0x30 > +#define ISELECT_IPRIO15 0x3f > +#define ISELECT_IMSIC_EIDELIVERY 0x70 > +#define ISELECT_IMSIC_EITHRESHOLD 0x72 > +#define ISELECT_IMSIC_EIP0 0x80 > +#define ISELECT_IMSIC_EIP63 0xbf > +#define ISELECT_IMSIC_EIE0 0xc0 > +#define ISELECT_IMSIC_EIE63 0xff > +#define ISELECT_IMSIC_FIRST ISELECT_IMSIC_EIDELIVERY > +#define ISELECT_IMSIC_LAST ISELECT_IMSIC_EIE63 > +#define ISELECT_MASK 0x1ff > + > +/* Dummy [M|S|VS]ISELECT value for emulating [M|S|VS]TOPEI CSRs */ > +#define ISELECT_IMSIC_TOPEI (ISELECT_MASK + 1) > + > +/* IMSIC bits (AIA) */ > +#define IMSIC_TOPEI_IID_SHIFT 16 > +#define IMSIC_TOPEI_IID_MASK 0x7ff > +#define IMSIC_TOPEI_IPRIO_MASK 0x7ff > +#define IMSIC_EIPx_BITS 32 > +#define IMSIC_EIEx_BITS 32 > + > +/* MTOPI and STOPI bits (AIA) */ > +#define TOPI_IID_SHIFT 16 > +#define TOPI_IID_MASK 0xfff > +#define TOPI_IPRIO_MASK 0xff > + > +/* Interrupt priority bits (AIA) */ > +#define IPRIO_IRQ_BITS 8 > +#define IPRIO_MMAXIPRIO 255 > +#define IPRIO_DEFAULT_MMAXIPRIO 15 > +#define IPRIO_DEFAULT_VS (IPRIO_DEFAULT_MMAXIPRIO - 4) > +#define IPRIO_DEFAULT_SGEXT (IPRIO_DEFAULT_MMAXIPRIO - 5) > +#define IPRIO_DEFAULT_S (IPRIO_DEFAULT_MMAXIPRIO - 6) > +#define IPRIO_DEFAULT_M (IPRIO_DEFAULT_MMAXIPRIO - 7) > +#define IPRIO_DEFAULT_U(_i) (((_i) >> 4) & 0x3) > +#define IPRIO_DEFAULT_L(_i) ((_i) & 0xf) > +#define IPRIO_DEFAULT_16_23(_i) \ > + (IPRIO_DEFAULT_MMAXIPRIO - (IPRIO_DEFAULT_L(_i) >> 1)) > +#define IPRIO_DEFAULT_24_31(_i) \ > + (IPRIO_DEFAULT_MMAXIPRIO - (4 + (IPRIO_DEFAULT_L(_i) >> 1))) > +#define IPRIO_DEFAULT_32_47(_i) \ > + (IPRIO_DEFAULT_MMAXIPRIO - (IPRIO_DEFAULT_L(_i) >> 2)) > +#define IPRIO_DEFAULT_48_63(_i) \ > + (IPRIO_DEFAULT_MMAXIPRIO - (8 + (IPRIO_DEFAULT_L(_i) >> 2))) > + > +/* HVICTL bits (AIA) */ > +#define HVICTL_VTI 0x40000000 > +#define HVICTL_IID 0x0fff0000 > +#define HVICTL_IPRIOM 0x00000100 > +#define HVICTL_IPRIO 0x000000ff > +#define HVICTL_VALID_MASK \ > + (HVICTL_VTI | HVICTL_IID | HVICTL_IPRIOM | HVICTL_IPRIO) > + > #endif > -- > 2.25.1 > >
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 0c6ef6e51c..5b28e73506 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -160,6 +160,31 @@ #define CSR_MTVAL 0x343 #define CSR_MIP 0x344 +/* Machine-Level Window to Indirectly Accessed Registers (AIA) */ +#define CSR_MISELECT 0x350 +#define CSR_MIREG 0x351 + +/* Machine-Level Interrupts (AIA) */ +#define CSR_MTOPI 0xfb0 + +/* Machine-Level IMSIC Interface (AIA) */ +#define CSR_MSETEIPNUM 0x358 +#define CSR_MCLREIPNUM 0x359 +#define CSR_MSETEIENUM 0x35a +#define CSR_MCLREIENUM 0x35b +#define CSR_MTOPEI 0x35c + +/* Virtual Interrupts for Supervisor Level (AIA) */ +#define CSR_MVIEN 0x308 +#define CSR_MVIP 0x309 + +/* Machine-Level High-Half CSRs (AIA) */ +#define CSR_MIDELEGH 0x313 +#define CSR_MIEH 0x314 +#define CSR_MVIENH 0x318 +#define CSR_MVIPH 0x319 +#define CSR_MIPH 0x354 + /* Supervisor Trap Setup */ #define CSR_SSTATUS 0x100 #define CSR_SEDELEG 0x102 @@ -179,6 +204,24 @@ #define CSR_SPTBR 0x180 #define CSR_SATP 0x180 +/* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ +#define CSR_SISELECT 0x150 +#define CSR_SIREG 0x151 + +/* Supervisor-Level Interrupts (AIA) */ +#define CSR_STOPI 0xdb0 + +/* Supervisor-Level IMSIC Interface (AIA) */ +#define CSR_SSETEIPNUM 0x158 +#define CSR_SCLREIPNUM 0x159 +#define CSR_SSETEIENUM 0x15a +#define CSR_SCLREIENUM 0x15b +#define CSR_STOPEI 0x15c + +/* Supervisor-Level High-Half CSRs (AIA) */ +#define CSR_SIEH 0x114 +#define CSR_SIPH 0x154 + /* Hpervisor CSRs */ #define CSR_HSTATUS 0x600 #define CSR_HEDELEG 0x602 @@ -209,6 +252,35 @@ #define CSR_MTINST 0x34a #define CSR_MTVAL2 0x34b +/* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */ +#define CSR_HVIEN 0x608 +#define CSR_HVICTL 0x609 +#define CSR_HVIPRIO1 0x646 +#define CSR_HVIPRIO2 0x647 + +/* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */ +#define CSR_VSISELECT 0x250 +#define CSR_VSIREG 0x251 + +/* VS-Level Interrupts (H-extension with AIA) */ +#define CSR_VSTOPI 0xeb0 + +/* VS-Level IMSIC Interface (H-extension with AIA) */ +#define CSR_VSSETEIPNUM 0x258 +#define CSR_VSCLREIPNUM 0x259 +#define CSR_VSSETEIENUM 0x25a +#define CSR_VSCLREIENUM 0x25b +#define CSR_VSTOPEI 0x25c + +/* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */ +#define CSR_HIDELEGH 0x613 +#define CSR_HVIENH 0x618 +#define CSR_HVIPH 0x655 +#define CSR_HVIPRIO1H 0x656 +#define CSR_HVIPRIO2H 0x657 +#define CSR_VSIEH 0x214 +#define CSR_VSIPH 0x254 + /* Enhanced Physical Memory Protection (ePMP) */ #define CSR_MSECCFG 0x747 #define CSR_MSECCFGH 0x757 @@ -619,4 +691,59 @@ typedef enum RISCVException { #define UMTE_U_PM_INSN U_PM_INSN #define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_INSN) +/* MISELECT, SISELECT, and VSISELECT bits (AIA) */ +#define ISELECT_IPRIO0 0x30 +#define ISELECT_IPRIO15 0x3f +#define ISELECT_IMSIC_EIDELIVERY 0x70 +#define ISELECT_IMSIC_EITHRESHOLD 0x72 +#define ISELECT_IMSIC_EIP0 0x80 +#define ISELECT_IMSIC_EIP63 0xbf +#define ISELECT_IMSIC_EIE0 0xc0 +#define ISELECT_IMSIC_EIE63 0xff +#define ISELECT_IMSIC_FIRST ISELECT_IMSIC_EIDELIVERY +#define ISELECT_IMSIC_LAST ISELECT_IMSIC_EIE63 +#define ISELECT_MASK 0x1ff + +/* Dummy [M|S|VS]ISELECT value for emulating [M|S|VS]TOPEI CSRs */ +#define ISELECT_IMSIC_TOPEI (ISELECT_MASK + 1) + +/* IMSIC bits (AIA) */ +#define IMSIC_TOPEI_IID_SHIFT 16 +#define IMSIC_TOPEI_IID_MASK 0x7ff +#define IMSIC_TOPEI_IPRIO_MASK 0x7ff +#define IMSIC_EIPx_BITS 32 +#define IMSIC_EIEx_BITS 32 + +/* MTOPI and STOPI bits (AIA) */ +#define TOPI_IID_SHIFT 16 +#define TOPI_IID_MASK 0xfff +#define TOPI_IPRIO_MASK 0xff + +/* Interrupt priority bits (AIA) */ +#define IPRIO_IRQ_BITS 8 +#define IPRIO_MMAXIPRIO 255 +#define IPRIO_DEFAULT_MMAXIPRIO 15 +#define IPRIO_DEFAULT_VS (IPRIO_DEFAULT_MMAXIPRIO - 4) +#define IPRIO_DEFAULT_SGEXT (IPRIO_DEFAULT_MMAXIPRIO - 5) +#define IPRIO_DEFAULT_S (IPRIO_DEFAULT_MMAXIPRIO - 6) +#define IPRIO_DEFAULT_M (IPRIO_DEFAULT_MMAXIPRIO - 7) +#define IPRIO_DEFAULT_U(_i) (((_i) >> 4) & 0x3) +#define IPRIO_DEFAULT_L(_i) ((_i) & 0xf) +#define IPRIO_DEFAULT_16_23(_i) \ + (IPRIO_DEFAULT_MMAXIPRIO - (IPRIO_DEFAULT_L(_i) >> 1)) +#define IPRIO_DEFAULT_24_31(_i) \ + (IPRIO_DEFAULT_MMAXIPRIO - (4 + (IPRIO_DEFAULT_L(_i) >> 1))) +#define IPRIO_DEFAULT_32_47(_i) \ + (IPRIO_DEFAULT_MMAXIPRIO - (IPRIO_DEFAULT_L(_i) >> 2)) +#define IPRIO_DEFAULT_48_63(_i) \ + (IPRIO_DEFAULT_MMAXIPRIO - (8 + (IPRIO_DEFAULT_L(_i) >> 2))) + +/* HVICTL bits (AIA) */ +#define HVICTL_VTI 0x40000000 +#define HVICTL_IID 0x0fff0000 +#define HVICTL_IPRIOM 0x00000100 +#define HVICTL_IPRIO 0x000000ff +#define HVICTL_VALID_MASK \ + (HVICTL_VTI | HVICTL_IID | HVICTL_IPRIOM | HVICTL_IPRIO) + #endif
The RISC-V AIA specification extends RISC-V local interrupts and introduces new CSRs. This patch adds defines for the new AIA CSRs. Signed-off-by: Anup Patel <anup.patel@wdc.com> --- target/riscv/cpu_bits.h | 127 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 127 insertions(+)