From patchwork Wed Dec 22 09:23:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Troy Lee X-Patchwork-Id: 12691345 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C3A13C433F5 for ; Wed, 22 Dec 2021 09:26:27 +0000 (UTC) Received: from localhost ([::1]:34330 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mzxtC-0003mA-ME for qemu-devel@archiver.kernel.org; Wed, 22 Dec 2021 04:26:26 -0500 Received: from eggs.gnu.org ([209.51.188.92]:44764) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mzxqt-0001zR-1t for qemu-devel@nongnu.org; Wed, 22 Dec 2021 04:24:03 -0500 Received: from twspam01.aspeedtech.com ([211.20.114.71]:15856) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mzxqr-0002Pq-16 for qemu-devel@nongnu.org; Wed, 22 Dec 2021 04:24:02 -0500 Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 1BM9Ht34081427; Wed, 22 Dec 2021 17:17:55 +0800 (GMT-8) (envelope-from troy_lee@aspeedtech.com) Received: from localhost.localdomain (192.168.10.10) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 22 Dec 2021 17:23:21 +0800 From: Troy Lee To: , Subject: [PATCH v1 2/2] hw/arm/aspeed_ast2600: create i3c instance Date: Wed, 22 Dec 2021 17:23:19 +0800 Message-ID: <20211222092319.2988568-3-troy_lee@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211222092319.2988568-1-troy_lee@aspeedtech.com> References: <20211222092319.2988568-1-troy_lee@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.10.10] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 1BM9Ht34081427 Received-SPF: pass client-ip=211.20.114.71; envelope-from=troy_lee@aspeedtech.com; helo=twspam01.aspeedtech.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Andrew Jeffery , leetroy@gmail.com, "open list:ASPEED BMCs" , =?utf-8?q?C=C3=A9dric_Le_Goa?= =?utf-8?q?ter?= , Joel Stanley Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This patch includes i3c instance in ast2600 soc. Signed-off-by: Troy Lee --- hw/arm/aspeed_ast2600.c | 12 ++++++++++++ include/hw/arm/aspeed_soc.h | 3 +++ 2 files changed, 15 insertions(+) diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index f2fef9d706..219b025bc2 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -63,6 +63,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = { [ASPEED_DEV_VUART] = 0x1E787000, [ASPEED_DEV_FSI1] = 0x1E79B000, [ASPEED_DEV_FSI2] = 0x1E79B100, + [ASPEED_DEV_I3C] = 0x1E7A0000, [ASPEED_DEV_SDRAM] = 0x80000000, }; @@ -112,6 +113,7 @@ static const int aspeed_soc_ast2600_irqmap[] = { [ASPEED_DEV_FSI1] = 100, [ASPEED_DEV_FSI2] = 101, [ASPEED_DEV_DP] = 62, + [ASPEED_DEV_I3C] = 102, /* 102 -> 107 */ }; static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) @@ -230,6 +232,8 @@ static void aspeed_soc_ast2600_init(Object *obj) object_initialize_child(obj, "pwm", &s->pwm, TYPE_ASPEED_PWM); + object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C); + object_initialize_child(obj, "fsi[*]", &s->fsi[0], TYPE_ASPEED_APB2OPB); } @@ -542,6 +546,14 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->pwm), 0, aspeed_soc_get_irq(s, ASPEED_DEV_PWM)); + /* I3C */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c), 0, + aspeed_soc_get_irq(s, ASPEED_DEV_I3C)); + /* FSI */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->fsi[0]), errp)) { return; diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 0db200d813..0c950fab3c 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -21,6 +21,7 @@ #include "hw/timer/aspeed_timer.h" #include "hw/rtc/aspeed_rtc.h" #include "hw/i2c/aspeed_i2c.h" +#include "hw/misc/aspeed_i3c.h" #include "hw/ssi/aspeed_smc.h" #include "hw/misc/aspeed_hace.h" #include "hw/watchdog/wdt_aspeed.h" @@ -53,6 +54,7 @@ struct AspeedSoCState { AspeedRtcState rtc; AspeedTimerCtrlState timerctrl; AspeedI2CState i2c; + AspeedI3CState i3c; AspeedSCUState scu; AspeedHACEState hace; AspeedXDMAState xdma; @@ -148,6 +150,7 @@ enum { ASPEED_DEV_FSI2, ASPEED_DEV_DPMCU, ASPEED_DEV_DP, + ASPEED_DEV_I3C, }; #endif /* ASPEED_SOC_H */