| Message ID | 20211224034915.17204-2-liweiwei@iscas.ac.cn (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | support subsets of Float-Point in Integer Registers extensions | expand |
On 12/23/21 7:49 PM, liweiwei wrote: > Co-authored-by: ardxwe<ardxwe@gmail.com> > Signed-off-by: liweiwei<liweiwei@iscas.ac.cn> > Signed-off-by: wangjunqiang<wangjunqiang@iscas.ac.cn> > --- > roms/SLOF | 2 +- > target/riscv/cpu.c | 12 ++++++++++++ > target/riscv/cpu.h | 4 ++++ > target/riscv/translate.c | 8 ++++++++ > 4 files changed, 25 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
On Fri, Dec 24, 2021 at 1:51 PM liweiwei <liweiwei@iscas.ac.cn> wrote: > > Co-authored-by: ardxwe <ardxwe@gmail.com> > Signed-off-by: liweiwei <liweiwei@iscas.ac.cn> > Signed-off-by: wangjunqiang <wangjunqiang@iscas.ac.cn> > --- > roms/SLOF | 2 +- > target/riscv/cpu.c | 12 ++++++++++++ > target/riscv/cpu.h | 4 ++++ > target/riscv/translate.c | 8 ++++++++ > 4 files changed, 25 insertions(+), 1 deletion(-) > > diff --git a/roms/SLOF b/roms/SLOF > index a6906b024c..dd0dcaa1c1 160000 > --- a/roms/SLOF > +++ b/roms/SLOF > @@ -1 +1 @@ > -Subproject commit a6906b024c6cca5a86496f51eb4bfee3a0c36148 > +Subproject commit dd0dcaa1c1085c159ddab709c7f274b3917be8bd It looks like you accidentally changed a submodule. Alistair
diff --git a/roms/SLOF b/roms/SLOF index a6906b024c..dd0dcaa1c1 160000 --- a/roms/SLOF +++ b/roms/SLOF @@ -1 +1 @@ -Subproject commit a6906b024c6cca5a86496f51eb4bfee3a0c36148 +Subproject commit dd0dcaa1c1085c159ddab709c7f274b3917be8bd diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6ef3314bce..a5fa14f2ac 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -491,6 +491,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) cpu->cfg.ext_d = true; } + if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || + cpu->cfg.ext_zhinxmin ) { + cpu->cfg.ext_zfinx = true; + } + /* Set the ISA extensions, checks should have happened above */ if (cpu->cfg.ext_i) { ext |= RVI; @@ -565,6 +570,13 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) if (cpu->cfg.ext_j) { ext |= RVJ; } + if (cpu->cfg.ext_zfinx && ((ext & (RVF | RVD)) || cpu->cfg.ext_zfh || + cpu->cfg.ext_zfhmin)) { + error_setg(errp, + "'Zfinx' cannot be supported together with 'F', 'D', 'Zfh'," + " 'Zfhmin'"); + return; + } set_misa(env, env->misa_mxl, ext); } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index dc10f27093..6fba31c5cd 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -315,8 +315,12 @@ struct RISCVCPU { bool ext_counters; bool ext_ifencei; bool ext_icsr; + bool ext_zdinx; bool ext_zfh; bool ext_zfhmin; + bool ext_zfinx; + bool ext_zhinx; + bool ext_zhinxmin; char *priv_spec; char *user_spec; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 5df6c0d800..8b1cdacf50 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -76,8 +76,12 @@ typedef struct DisasContext { RISCVMXL ol; bool virt_enabled; bool ext_ifencei; + bool ext_zdinx; bool ext_zfh; bool ext_zfhmin; + bool ext_zfinx; + bool ext_zhinx; + bool ext_zhinxmin; bool hlsx; /* vector extension */ bool vill; @@ -703,8 +707,12 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->misa_ext = env->misa_ext; ctx->frm = -1; /* unknown rounding mode */ ctx->ext_ifencei = cpu->cfg.ext_ifencei; + ctx->ext_zdinx = cpu->cfg.ext_zdinx; ctx->ext_zfh = cpu->cfg.ext_zfh; ctx->ext_zfhmin = cpu->cfg.ext_zfhmin; + ctx->ext_zfinx = cpu->cfg.ext_zfinx; + ctx->ext_zhinx = cpu->cfg.ext_zhinx; + ctx->ext_zhinxmin = cpu->cfg.ext_zhinxmin; ctx->vlen = cpu->cfg.vlen; ctx->elen = cpu->cfg.elen; ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);