Message ID | 20211224034915.17204-7-liweiwei@iscas.ac.cn (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | support subsets of Float-Point in Integer Registers extensions | expand |
On 12/23/21 7:49 PM, liweiwei wrote: > Co-authored-by: ardxwe <ardxwe@gmail.com> > Signed-off-by: liweiwei <liweiwei@iscas.ac.cn> > Signed-off-by: wangjunqiang <wangjunqiang@iscas.ac.cn> > --- > target/riscv/cpu.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index a5fa14f2ac..dbd15693be 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -657,6 +657,10 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), > DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), > DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), > + DEFINE_PROP_BOOL("Zdinx", RISCVCPU, cfg.ext_zdinx, false), > + DEFINE_PROP_BOOL("Zfinx", RISCVCPU, cfg.ext_zfinx, false), > + DEFINE_PROP_BOOL("Zhinx", RISCVCPU, cfg.ext_zhinx, false), > + DEFINE_PROP_BOOL("Zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), > DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), > DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), > /* ePMP 0.9.3 */ > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a5fa14f2ac..dbd15693be 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -657,6 +657,10 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), + DEFINE_PROP_BOOL("Zdinx", RISCVCPU, cfg.ext_zdinx, false), + DEFINE_PROP_BOOL("Zfinx", RISCVCPU, cfg.ext_zfinx, false), + DEFINE_PROP_BOOL("Zhinx", RISCVCPU, cfg.ext_zhinx, false), + DEFINE_PROP_BOOL("Zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), /* ePMP 0.9.3 */